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History

[mlir][amdgpu] Shared memory access optimization pass (#75627 )

It implements transformation to optimize accesses to shared memory.

Reference: https://reviews.llvm.org/D127457

_This change adds a transformation and pass to the NvGPU dialect that
attempts to optimize reads/writes from a memref representing GPU shared
memory in order to avoid bank conflicts. Given a value representing a
shared memory memref, it traverses all reads/writes within the parent op
and, subject to suitable conditions, rewrites all last dimension index
values such that element locations in the final (col) dimension are
given by newColIdx = col % vecSize + perm[row](col / vecSize, row)
where perm is a permutation function indexed by row and vecSize
is the vector access size in elements (currently assumes 128bit
vectorized accesses, but this can be made a parameter). This specific
transformation can help optimize typical distributed & vectorized
accesses
common to loading matrix multiplication operands to/from shared memory._

2024-01-19 15:44:45 -08:00

benchmark/python

[mlir][benchmark] Fix broken benchmark script (#68841 )

2023-12-06 12:17:53 +05:30

cmake/modules

Revert "[mlir] Consider mlir-linalg-ods-gen as a tablegen tool in build (#75093 )"

2024-01-04 02:01:16 +05:00

docs

[mlir][docs] Fix broken link

2024-01-19 17:38:27 +01:00

examples

[mlir][IR] Rename "update root" to "modify op" in rewriter API (#78260 )