llvm-project/llvm/docs/AMDGPU/gfx10_vcc.rst
Dmitry Preobrazhensky 8ea3e9d9a2 [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- Added f16 omod modifier (bug 51386).
- Corrected names of data types (bug 48638).
- Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231).
- Corrected description of integer operands (bug 51130).
- Corrected description of 8-bit DS offsets (bug 51536).
- Improved PERMLANE op_sel description.
- Corrected *SAD* opcode types.
2021-08-27 17:23:20 +03:00

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.. _amdgpu_synid_gfx10_vcc:
vcc
===
Vector condition code. This operand depends on wavefront size:
* Should be :ref:`vcc_lo<amdgpu_synid_vcc_lo>` if wavefront size is 32.
* Should be :ref:`vcc<amdgpu_synid_vcc>` if wavefront size is 64.