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cc426402be
Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable abs and neg modifiers for v_cndmask_b32_e64. - Minor corrections and improvements.
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926 B
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29 lines
926 B
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..
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* *
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* Automatically generated file, do not edit! *
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* *
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.. _amdgpu_synid_gfx7_vsrc_ba3116:
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vsrc
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====
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Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
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The :ref:`compr<amdgpu_synid_compr>` modifier indicates the use of compressed (16-bit) data, thus decreasing the number of source operands from 4 to 2:
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* src0 and src1 must specify the first register (or :ref:`off<amdgpu_synid_off>`).
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* src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
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An example:
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.. parsed-literal::
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exp mrtz v3, v3, off, off compr
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*Size:* 1 dword.
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*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
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