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d8ac03f15e
Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469). - Enable abs and neg modifiers for v_cndmask_b32 (https://reviews.llvm.org/D135900). - Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable image_gather4h (https://reviews.llvm.org/D130764). - Minor corrections and improvements.
27 lines
898 B
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27 lines
898 B
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* Automatically generated file, do not edit! *
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.. _amdgpu_synid_gfx9_vdata_aa5a53:
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vdata
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=====
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Input data for an atomic instruction.
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Optionally, this operand may be used to store output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`:
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* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
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Note: the surface data format is indicated in the image resource constant, but not in the instruction.
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*Operands:* :ref:`v<amdgpu_synid_v>`
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