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4bfe410802
Conditions that need to be met: 1. count(StartAtCycle) == count(ReservedCycles); 2. For each i: StartAtCycles[i] < ReservedCycles[i]; 3. For each i: StartAtCycles[i] >= 0; 4. If left unspecified, the elements are set to 0. Differential Revision: https://reviews.llvm.org/D150310
87 lines
2.6 KiB
TableGen
87 lines
2.6 KiB
TableGen
// RUN: llvm-tblgen -gen-subtarget -DCORRECT -I %p/../../include %s 2>&1 | \
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// RUN: FileCheck %s --check-prefix=CORRECT
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// RUN: not llvm-tblgen -gen-subtarget -DWRONG_SIZE -I %p/../../include %s 2>&1 | \
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// RUN: FileCheck %s --check-prefix=WRONG_SIZE
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// RUN: not llvm-tblgen -gen-subtarget -DWRONG_VALUE -I %p/../../include %s 2>&1 | \
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// RUN: FileCheck %s --check-prefix=WRONG_VALUE
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// RUN: not llvm-tblgen -gen-subtarget -DNEGATIVE_INVALID -I %p/../../include %s 2>&1 | \
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// RUN: FileCheck %s --check-prefix=NEGATIVE_INVALID
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// Make sure that StartAtCycle in WriteRes is used to generate the
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// correct data.
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include "llvm/Target/Target.td"
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def MyTarget : Target;
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let BufferSize = 0 in {
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def ResX0 : ProcResource<1>; // X0
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def ResX1 : ProcResource<1>; // X1
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def ResX2 : ProcResource<1>; // X2
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}
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let OutOperandList = (outs), InOperandList = (ins) in {
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def Inst_A : Instruction;
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def Inst_B : Instruction;
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}
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let CompleteModel = 0 in {
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def SchedModel_A: SchedMachineModel;
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}
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def WriteInst_A : SchedWrite;
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def WriteInst_B : SchedWrite;
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let SchedModel = SchedModel_A in {
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// Check the generated data when there are no semantic issues.
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#ifdef CORRECT
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// CORRECT-LABEL: llvm::MCWriteProcResEntry MyTargetWriteProcResTable[] = {
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// CORRECT-NEXT: { 0, 0, 0 }, // Invalid
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def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {
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// CORRECT-NEXT: { 1, 2, 0}, // #1
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// CORRECT-NEXT: { 2, 4, 1}, // #2
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// CORRECT-NEXT: { 3, 3, 2}, // #3
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let ResourceCycles = [2, 4, 3];
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let StartAtCycles = [0, 1, 2];
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}
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def : WriteRes<WriteInst_B, [ResX2]> {
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// If unspecified, StartAtCycle is set to 0.
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// CORRECT-NEXT: { 3, 1, 0} // #4
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let ResourceCycles = [1];
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}
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#endif // CORRECT
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#ifdef WRONG_SIZE
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// WRONG_SIZE: StartAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: size(StartAtCycles) != size(ProcResources): 2 vs 3
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def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {
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let ResourceCycles = [2, 4, 3];
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let StartAtCycles = [0, 1];
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}
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#endif
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#ifdef WRONG_VALUE
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// WRONG_VALUE: StartAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: StartAtCycles < Cycles must hold
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def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {
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let ResourceCycles = [2, 4, 3];
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let StartAtCycles = [0, 1, 8];
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}
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#endif
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#ifdef NEGATIVE_INVALID
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// NEGATIVE_INVALID: StartAtCycle.td:[[@LINE+1]]:1: error: Invalid value: StartAtCycle must be a non-negative value.
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def : WriteRes<WriteInst_A, [ResX0]> {
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let ResourceCycles = [2];
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let StartAtCycles = [-1];
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}
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#endif
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def : InstRW<[WriteInst_A], (instrs Inst_A)>;
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def : InstRW<[WriteInst_B], (instrs Inst_B)>;
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}
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def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;
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