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6bec3e9303
Most clients only used these methods because they wanted to be able to extend or truncate to the same bit width (which is a no-op). Now that the standard zext, sext and trunc allow this, there is no reason to use the OrSelf versions. The OrSelf versions additionally have the strange behaviour of allowing extending to a *smaller* width, or truncating to a *larger* width, which are also treated as no-ops. A small amount of client code relied on this (ConstantRange::castOp and MicrosoftCXXNameMangler::mangleNumber) and needed rewriting. Differential Revision: https://reviews.llvm.org/D125557
102 lines
3.4 KiB
TableGen
102 lines
3.4 KiB
TableGen
// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
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// Check if VarLenCodeEmitterGen works correctly.
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include "llvm/Target/Target.td"
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def ArchInstrInfo : InstrInfo { }
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def Arch : Target {
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let InstructionSet = ArchInstrInfo;
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}
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def Reg : Register<"reg">;
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def RegClass : RegisterClass<"foo", [i64], 0, (add Reg)>;
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def GR64 : RegisterOperand<RegClass>;
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class MyMemOperand<dag sub_ops> : Operand<iPTR> {
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let MIOperandInfo = sub_ops;
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dag Base;
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dag Extension;
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}
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class MyVarInst<MyMemOperand memory_op> : Instruction {
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dag Inst;
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let OutOperandList = (outs GR64:$dst);
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let InOperandList = (ins memory_op:$src);
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// Testing `ascend` and `descend`
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let Inst = (ascend
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(descend 0b10110111, memory_op.Base),
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memory_op.Extension,
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// Testing operand referencing.
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(operand "$dst", 4),
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// Testing operand referencing with a certain bit range.
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(slice "$dst", 3, 1),
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// Testing custom encoder
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(operand "$dst", 2, (encoder "myCustomEncoder"))
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);
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}
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class MemOp16<string op_name> : MyMemOperand<(ops GR64:$reg, i16imm:$offset)> {
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// Testing sub-operand referencing.
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let Base = (operand "$"#op_name#".reg", 8);
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let Extension = (operand "$"#op_name#".offset", 16);
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}
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class MemOp32<string op_name> : MyMemOperand<(ops GR64:$reg, i32imm:$offset)> {
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let Base = (operand "$"#op_name#".reg", 8);
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// Testing variable-length instruction encoding.
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let Extension = (operand "$"#op_name#".offset", 32);
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}
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def FOO16 : MyVarInst<MemOp16<"src">>;
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def FOO32 : MyVarInst<MemOp32<"src">>;
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// The fixed bits part
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// CHECK: {/*NumBits*/41,
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// CHECK-SAME: // FOO16
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// CHECK: {/*NumBits*/57,
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// CHECK-SAME: // FOO32
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// CHECK: UINT64_C(46848), // FOO16
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// CHECK: UINT64_C(46848), // FOO32
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// CHECK-LABEL: case ::FOO16: {
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// CHECK: Scratch = Scratch.zext(41);
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// src.reg
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// CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);
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// CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0);
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// src.offset
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// CHECK: getMachineOpValue(MI, MI.getOperand(2), /*Pos=*/16, Scratch, Fixups, STI);
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// CHECK: Inst.insertBits(Scratch.extractBits(16, 0), 16);
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// 1st dst
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// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/32, Scratch, Fixups, STI);
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// CHECK: Inst.insertBits(Scratch.extractBits(4, 0), 32);
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// 2nd dst
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// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/36, Scratch, Fixups, STI);
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// CHECK: Inst.insertBits(Scratch.extractBits(3, 1), 36);
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// dst w/ custom encoder
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// CHECK: myCustomEncoder(MI, /*OpIdx=*/0, /*Pos=*/39, Scratch, Fixups, STI);
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// CHECK: Inst.insertBits(Scratch.extractBits(2, 0), 39);
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// CHECK-LABEL: case ::FOO32: {
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// CHECK: Scratch = Scratch.zext(57);
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// src.reg
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// CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);
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// CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0);
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// src.offset
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// CHECK: getMachineOpValue(MI, MI.getOperand(2), /*Pos=*/16, Scratch, Fixups, STI);
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// CHECK: Inst.insertBits(Scratch.extractBits(32, 0), 16);
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// 1st dst
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// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/48, Scratch, Fixups, STI);
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// CHECK: Inst.insertBits(Scratch.extractBits(4, 0), 48);
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// 2nd dst
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// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/52, Scratch, Fixups, STI);
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// CHECK: Inst.insertBits(Scratch.extractBits(3, 1), 52);
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// dst w/ custom encoder
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// CHECK: myCustomEncoder(MI, /*OpIdx=*/0, /*Pos=*/55, Scratch, Fixups, STI);
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// CHECK: Inst.insertBits(Scratch.extractBits(2, 0), 55);
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