mirror of
https://github.com/llvm/llvm-project.git
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c0b2c10e9f
Set the default processor version to v68 when the user does not specify one in the command line. This includes changes in the LLVM backed and linker (lld). Since lld normally sets the version based on inputs, this change will only affect cases when there are no inputs. Fixes #127558
340 lines
9.5 KiB
LLVM
340 lines
9.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=hexagon < %s | FileCheck %s
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define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) {
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; CHECK-LABEL: atomicrmw_usub_cond_i8:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = and(#24,asl(r0,#3))
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; CHECK-NEXT: r3 = and(r0,#-4)
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; CHECK-NEXT: r2 = #255
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; CHECK-NEXT: r4 = and(r1,#255)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = asl(r2,r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5 = sub(#-1,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_1: // %atomicrmw.start
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: {
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; CHECK-NEXT: r6 = memw_locked(r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = lsr(r6,r0)
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; CHECK-NEXT: r6 = and(r6,r5)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r7 = and(r2,#255)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = cmp.gtu(r4,r7)
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; CHECK-NEXT: if (p0.new) r7 = add(r2,#0)
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; CHECK-NEXT: if (!p0.new) r7 = sub(r2,r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r7 = and(r7,#255)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r6 |= asl(r7,r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: memw_locked(r3,p0) = r6
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (!p0) jump:nt .LBB0_1
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; CHECK-NEXT: }
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; CHECK-NEXT: // %bb.2: // %atomicrmw.end
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = r2
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%result = atomicrmw usub_cond ptr %ptr, i8 %val seq_cst
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ret i8 %result
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}
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define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) {
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; CHECK-LABEL: atomicrmw_usub_cond_i16:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = and(#24,asl(r0,#3))
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; CHECK-NEXT: r3 = and(r0,#-4)
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; CHECK-NEXT: r2 = ##65535
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = asl(r2,r0)
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; CHECK-NEXT: r4 = zxth(r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5 = sub(#-1,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB1_1: // %atomicrmw.start
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: {
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; CHECK-NEXT: r6 = memw_locked(r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = lsr(r6,r0)
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; CHECK-NEXT: r6 = and(r6,r5)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r7 = zxth(r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = cmp.gtu(r4,r7)
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; CHECK-NEXT: if (p0.new) r7 = add(r2,#0)
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; CHECK-NEXT: if (!p0.new) r7 = sub(r2,r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r7 = zxth(r7)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r6 |= asl(r7,r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: memw_locked(r3,p0) = r6
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (!p0) jump:nt .LBB1_1
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; CHECK-NEXT: }
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; CHECK-NEXT: // %bb.2: // %atomicrmw.end
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = r2
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%result = atomicrmw usub_cond ptr %ptr, i16 %val seq_cst
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ret i16 %result
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}
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define i32 @atomicrmw_usub_cond_i32(ptr %ptr, i32 %val) {
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; CHECK-LABEL: atomicrmw_usub_cond_i32:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB2_1: // %atomicrmw.start
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = memw_locked(r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = cmp.gtu(r1,r2)
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; CHECK-NEXT: if (p0.new) r3 = add(r2,#0)
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; CHECK-NEXT: if (!p0.new) r3 = sub(r2,r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: memw_locked(r0,p0) = r3
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (!p0) jump:nt .LBB2_1
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; CHECK-NEXT: }
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; CHECK-NEXT: // %bb.2: // %atomicrmw.end
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = r2
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%result = atomicrmw usub_cond ptr %ptr, i32 %val seq_cst
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ret i32 %result
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}
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define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) {
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; CHECK-LABEL: atomicrmw_usub_cond_i64:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB3_1: // %atomicrmw.start
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: {
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; CHECK-NEXT: r5:4 = memd_locked(r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = cmp.gtu(r3:2,r5:4)
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; CHECK-NEXT: r7:6 = sub(r5:4,r3:2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r8 = mux(p0,r4,r6)
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; CHECK-NEXT: r9 = mux(p0,r5,r7)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: memd_locked(r0,p0) = r9:8
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (!p0) jump:nt .LBB3_1
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; CHECK-NEXT: }
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; CHECK-NEXT: // %bb.2: // %atomicrmw.end
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; CHECK-NEXT: {
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; CHECK-NEXT: r1:0 = combine(r5,r4)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%result = atomicrmw usub_cond ptr %ptr, i64 %val seq_cst
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ret i64 %result
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}
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define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) {
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; CHECK-LABEL: atomicrmw_usub_sat_i8:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = and(#24,asl(r0,#3))
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; CHECK-NEXT: r2 = and(r0,#-4)
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; CHECK-NEXT: r3 = #255
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; CHECK-NEXT: r1 = and(r1,#255)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r3 = asl(r3,r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r3 = sub(#-1,r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB4_1: // %atomicrmw.start
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: {
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; CHECK-NEXT: r5 = #255
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; CHECK-NEXT: r4 = memw_locked(r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5 &= lsr(r4,r0)
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; CHECK-NEXT: r6 = and(r4,r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5 = maxu(r5,r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5 = sub(r5,r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r6 |= asl(r5,r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: memw_locked(r2,p0) = r6
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (!p0) jump:nt .LBB4_1
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; CHECK-NEXT: }
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; CHECK-NEXT: // %bb.2: // %atomicrmw.end
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = lsr(r4,r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%result = atomicrmw usub_sat ptr %ptr, i8 %val seq_cst
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ret i8 %result
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}
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define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) {
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; CHECK-LABEL: atomicrmw_usub_sat_i16:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = and(#24,asl(r0,#3))
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; CHECK-NEXT: r2 = and(r0,#-4)
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; CHECK-NEXT: r3 = ##65535
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r3 = asl(r3,r0)
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; CHECK-NEXT: r1 = zxth(r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r3 = sub(#-1,r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB5_1: // %atomicrmw.start
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: {
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; CHECK-NEXT: r5 = ##65535
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; CHECK-NEXT: r4 = memw_locked(r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5 &= lsr(r4,r0)
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; CHECK-NEXT: r6 = and(r4,r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5 = maxu(r5,r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5 = sub(r5,r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r6 |= asl(r5,r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: memw_locked(r2,p0) = r6
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (!p0) jump:nt .LBB5_1
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; CHECK-NEXT: }
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; CHECK-NEXT: // %bb.2: // %atomicrmw.end
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = lsr(r4,r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%result = atomicrmw usub_sat ptr %ptr, i16 %val seq_cst
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ret i16 %result
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}
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define i32 @atomicrmw_usub_sat_i32(ptr %ptr, i32 %val) {
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; CHECK-LABEL: atomicrmw_usub_sat_i32:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB6_1: // %atomicrmw.start
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = memw_locked(r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r3 = maxu(r2,r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r3 = sub(r3,r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: memw_locked(r0,p0) = r3
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (!p0) jump:nt .LBB6_1
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; CHECK-NEXT: }
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; CHECK-NEXT: // %bb.2: // %atomicrmw.end
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = r2
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%result = atomicrmw usub_sat ptr %ptr, i32 %val seq_cst
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ret i32 %result
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}
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define i64 @atomicrmw_usub_sat_i64(ptr %ptr, i64 %val) {
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; CHECK-LABEL: atomicrmw_usub_sat_i64:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB7_1: // %atomicrmw.start
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: {
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; CHECK-NEXT: r5:4 = memd_locked(r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r7:6 = maxu(r5:4,r3:2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r7:6 = sub(r7:6,r3:2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: memd_locked(r0,p0) = r7:6
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (!p0) jump:nt .LBB7_1
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; CHECK-NEXT: }
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; CHECK-NEXT: // %bb.2: // %atomicrmw.end
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; CHECK-NEXT: {
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; CHECK-NEXT: r1:0 = combine(r5,r4)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%result = atomicrmw usub_sat ptr %ptr, i64 %val seq_cst
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ret i64 %result
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}
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