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37e6f84026
Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable abs and neg modifiers for v_cndmask_b32_dpp (https://reviews.llvm.org/D135900). - Enable literal operands for permlane16/permlanex16 (https://reviews.llvm.org/D137332). - Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469). - Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable image_gather4h (https://reviews.llvm.org/D130764). - Minor corrections and improvements.
21 lines
670 B
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21 lines
670 B
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* Automatically generated file, do not edit! *
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.. _amdgpu_synid_gfx10_vdst_dfa6da:
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vdst
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====
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Image data to be loaded by an image instruction.
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*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
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* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies 1 dword.
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* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
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*Operands:* :ref:`v<amdgpu_synid_v>`
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