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c253e5c991
This patch adds initial vector extension support to RISC-V's exegesis. The strategy here is to enumerate all RVV _pseudo_ opcodes as their MC opcode counterparts are kind of useless under this circumstance. We also enumerate all possible VTYPE operands in each CodeTemplate configuration. Various of MachineFunction Passes are used for post processing the snippets, like inserting VSETVLI instructions. See https://llvm.org/devmtg/2024-10/slides/techtalk/Hsu-RVV-Exegesis.pdf for more technical details.
86 lines
2.6 KiB
C++
86 lines
2.6 KiB
C++
//===- RISCVExegesisPreprocessing.cpp -------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// \file
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVExegesisPasses.h"
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#include "RISCVRegisterInfo.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-exegesis-preprocessing"
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namespace {
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struct RISCVExegesisPreprocessing : public MachineFunctionPass {
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static char ID;
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RISCVExegesisPreprocessing() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // anonymous namespace
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char RISCVExegesisPreprocessing::ID = 0;
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static bool processAVLOperand(MachineInstr &MI, MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII) {
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const MCInstrDesc &Desc = TII.get(MI.getOpcode());
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uint64_t TSFlags = Desc.TSFlags;
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if (!RISCVII::hasVLOp(TSFlags))
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return false;
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const MachineOperand &VLOp = MI.getOperand(RISCVII::getVLOpNum(Desc));
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if (VLOp.isReg()) {
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Register VLReg = VLOp.getReg();
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if (VLReg.isVirtual())
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return false;
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assert(RISCV::GPRRegClass.contains(VLReg));
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// Replace all uses of the original physical register with a new virtual
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// register. The only reason we can do such replacement here is because it's
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// almost certain that VLReg only has a single definition.
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Register NewVLReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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MRI.replaceRegWith(VLReg, NewVLReg);
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return true;
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}
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return false;
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}
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bool RISCVExegesisPreprocessing::runOnMachineFunction(MachineFunction &MF) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const auto &STI = MF.getSubtarget<RISCVSubtarget>();
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if (!STI.hasVInstructions())
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return false;
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const TargetInstrInfo &TII = *STI.getInstrInfo();
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LLVM_DEBUG(MF.print(dbgs() << "===Before RISCVExegesisPoreprocessing===\n");
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dbgs() << "\n");
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bool Changed = false;
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for (auto &MBB : MF)
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for (auto &MI : MBB) {
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Changed |= processAVLOperand(MI, MRI, TII);
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}
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return Changed;
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}
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FunctionPass *llvm::exegesis::createRISCVPreprocessingPass() {
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return new RISCVExegesisPreprocessing();
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}
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