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26fdad031c
This is a follow-on to https://reviews.llvm.org/D134073. The number of MIPS16 changes here is a bit surprising. Many of the fields with mismatched names were NOT previously choosing the correct argument positionally, but instead doing something completely wrong (e.g. it would encode a register where an immediate was expected). But, machine-code generation for MIPS16 has never actually functioned. It's also fully untested, thus, the MIPS16 changes, despite changing behavior, breaks (and fixes) zero tests. This change does not fix MIPS16 output, but it ought to be at least incrementally less broken. Outside MIPS16, I believe the only functional change is to the 'ginvi' instruction: it was previously encoding garbage into a field which was specified to be '00'. Fortunately, it was covered by tests -- and the tests were testing the incorrect behavior. So, fixed. Differential Revision: https://reviews.llvm.org/D134220
289 lines
14 KiB
TableGen
289 lines
14 KiB
TableGen
//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// This is the top level entry point for the Mips target.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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// The overall idea of the PredicateControl class is to chop the Predicates list
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// into subsets that are usually overridden independently. This allows
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// subclasses to partially override the predicates of their superclasses without
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// having to re-add all the existing predicates.
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class PredicateControl {
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// Predicates for the encoding scheme in use such as HasStdEnc
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list<Predicate> EncodingPredicates = [];
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// Predicates for the GPR size such as IsGP64bit
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list<Predicate> GPRPredicates = [];
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// Predicates for the PTR size such as IsPTR64bit
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list<Predicate> PTRPredicates = [];
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// Predicates for a symbol's size such as hasSym32.
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list<Predicate> SYMPredicates = [];
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// Predicates for the FGR size and layout such as IsFP64bit
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list<Predicate> FGRPredicates = [];
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// Predicates for the instruction group membership such as ISA's.
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list<Predicate> InsnPredicates = [];
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// Predicate for the ASE that an instruction belongs to.
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list<Predicate> ASEPredicate = [];
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// Predicate for marking the instruction as usable in hard-float mode only.
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list<Predicate> HardFloatPredicate = [];
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// Predicates for anything else
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list<Predicate> AdditionalPredicates = [];
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list<Predicate> Predicates = !listconcat(EncodingPredicates,
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GPRPredicates,
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PTRPredicates,
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SYMPredicates,
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FGRPredicates,
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InsnPredicates,
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HardFloatPredicate,
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ASEPredicate,
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AdditionalPredicates);
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}
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// Like Requires<> but for the AdditionalPredicates list
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class AdditionalRequires<list<Predicate> preds> {
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list<Predicate> AdditionalPredicates = preds;
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}
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//===----------------------------------------------------------------------===//
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// Mips Subtarget features //
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//===----------------------------------------------------------------------===//
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def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
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"Disable SVR4-style position-independent code">;
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def FeaturePTR64Bit : SubtargetFeature<"ptr64", "IsPTR64bit", "true",
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"Pointers are 64-bit wide">;
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def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
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"General Purpose Registers are 64-bit wide">;
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def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
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"Support 64-bit FP registers">;
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def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
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"Support for FPXX">;
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def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
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"IEEE 754-2008 NaN encoding">;
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def FeatureAbs2008 : SubtargetFeature<"abs2008", "Abs2008", "true",
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"Disable IEEE 754-2008 abs.fmt mode">;
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def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
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"true", "Only supports single precision float">;
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def FeatureSoftFloat : SubtargetFeature<"soft-float", "IsSoftFloat", "true",
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"Does not support floating point instructions">;
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def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
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"Disable odd numbered single-precision "
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"registers">;
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def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
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"true", "Enable vector FPU instructions">;
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def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
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"Mips I ISA Support [highly experimental]">;
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def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
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"Mips II ISA Support [highly experimental]",
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[FeatureMips1]>;
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def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
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"Subset of MIPS-III that is also in MIPS32 "
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"[highly experimental]">;
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def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
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"Subset of MIPS-III that is also in MIPS32r2 "
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"[highly experimental]">;
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def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
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"MIPS III ISA Support [highly experimental]",
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[FeatureMips2, FeatureMips3_32,
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FeatureMips3_32r2, FeatureGP64Bit,
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FeatureFP64Bit]>;
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def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
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"Subset of MIPS-IV that is also in MIPS32 "
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"[highly experimental]">;
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def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
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"Subset of MIPS-IV that is also in MIPS32r2 "
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"[highly experimental]">;
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def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
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"Mips4", "MIPS IV ISA Support",
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[FeatureMips3, FeatureMips4_32,
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FeatureMips4_32r2]>;
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def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
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"Subset of MIPS-V that is also in MIPS32r2 "
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"[highly experimental]">;
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def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
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"MIPS V ISA Support [highly experimental]",
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[FeatureMips4, FeatureMips5_32r2]>;
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def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
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"Mips32 ISA Support",
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[FeatureMips2, FeatureMips3_32,
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FeatureMips4_32]>;
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def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
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"Mips32r2", "Mips32r2 ISA Support",
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[FeatureMips3_32r2, FeatureMips4_32r2,
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FeatureMips5_32r2, FeatureMips32]>;
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def FeatureMips32r3 : SubtargetFeature<"mips32r3", "MipsArchVersion",
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"Mips32r3", "Mips32r3 ISA Support",
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[FeatureMips32r2]>;
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def FeatureMips32r5 : SubtargetFeature<"mips32r5", "MipsArchVersion",
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"Mips32r5", "Mips32r5 ISA Support",
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[FeatureMips32r3]>;
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def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
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"Mips32r6",
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"Mips32r6 ISA Support [experimental]",
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[FeatureMips32r5, FeatureFP64Bit,
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FeatureNaN2008, FeatureAbs2008]>;
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def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
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"Mips64", "Mips64 ISA Support",
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[FeatureMips5, FeatureMips32]>;
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def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
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"Mips64r2", "Mips64r2 ISA Support",
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[FeatureMips64, FeatureMips32r2]>;
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def FeatureMips64r3 : SubtargetFeature<"mips64r3", "MipsArchVersion",
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"Mips64r3", "Mips64r3 ISA Support",
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[FeatureMips64r2, FeatureMips32r3]>;
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def FeatureMips64r5 : SubtargetFeature<"mips64r5", "MipsArchVersion",
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"Mips64r5", "Mips64r5 ISA Support",
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[FeatureMips64r3, FeatureMips32r5]>;
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def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
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"Mips64r6",
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"Mips64r6 ISA Support [experimental]",
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[FeatureMips32r6, FeatureMips64r5,
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FeatureNaN2008, FeatureAbs2008]>;
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def FeatureSym32 : SubtargetFeature<"sym32", "HasSym32", "true",
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"Symbols are 32 bit on Mips64">;
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def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
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"Mips16 mode">;
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def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
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def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
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"Mips DSP-R2 ASE", [FeatureDSP]>;
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def FeatureDSPR3
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: SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
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[ FeatureDSP, FeatureDSPR2 ]>;
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def FeatureMips3D : SubtargetFeature<"mips3d", "Has3D", "true", "Mips 3D ASE">;
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def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
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def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
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def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Mips R6 CRC ASE">;
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def FeatureVirt : SubtargetFeature<"virt", "HasVirt", "true",
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"Mips Virtualization ASE">;
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def FeatureGINV : SubtargetFeature<"ginv", "HasGINV", "true",
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"Mips Global Invalidate ASE">;
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def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
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"microMips mode">;
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def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
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"true", "Octeon cnMIPS Support",
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[FeatureMips64r2]>;
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def FeatureCnMipsP : SubtargetFeature<"cnmipsp", "HasCnMipsP",
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"true", "Octeon+ cnMIPS Support",
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[FeatureCnMips]>;
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def FeatureUseTCCInDIV : SubtargetFeature<
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"use-tcc-in-div",
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"UseTCCInDIV", "false",
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"Force the assembler to use trapping">;
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def FeatureNoMadd4
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: SubtargetFeature<"nomadd4", "DisableMadd4", "true",
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"Disable 4-operand madd.fmt and related instructions">;
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def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">;
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def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true",
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"Disable use of the jal instruction">;
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def FeatureXGOT
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: SubtargetFeature<"xgot", "UseXGOT", "true", "Assume 32-bit GOT">;
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def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard",
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"UseIndirectJumpsHazard",
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"true", "Use indirect jump"
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" guards to prevent certain speculation based attacks">;
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "MipsRegisterInfo.td"
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include "MipsSchedule.td"
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include "MipsInstrInfo.td"
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include "MipsCallingConv.td"
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include "MipsRegisterBanks.td"
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include "MipsCombine.td"
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// Avoid forward declaration issues.
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include "MipsScheduleP5600.td"
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include "MipsScheduleGeneric.td"
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def MipsInstrInfo : InstrInfo {
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}
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//===----------------------------------------------------------------------===//
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// Mips processors supported.
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//===----------------------------------------------------------------------===//
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def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
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"MipsSubtarget::CPU::P5600",
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"The P5600 Processor", [FeatureMips32r5]>;
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class Proc<string Name, list<SubtargetFeature> Features>
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: ProcessorModel<Name, MipsGenericModel, Features>;
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def : Proc<"generic", [FeatureMips32]>;
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def : Proc<"mips1", [FeatureMips1]>;
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def : Proc<"mips2", [FeatureMips2]>;
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def : Proc<"mips32", [FeatureMips32]>;
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def : Proc<"mips32r2", [FeatureMips32r2]>;
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def : Proc<"mips32r3", [FeatureMips32r3]>;
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def : Proc<"mips32r5", [FeatureMips32r5]>;
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def : Proc<"mips32r6", [FeatureMips32r6]>;
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def : Proc<"mips3", [FeatureMips3]>;
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def : Proc<"mips4", [FeatureMips4]>;
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def : Proc<"mips5", [FeatureMips5]>;
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def : Proc<"mips64", [FeatureMips64]>;
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def : Proc<"mips64r2", [FeatureMips64r2]>;
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def : Proc<"mips64r3", [FeatureMips64r3]>;
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def : Proc<"mips64r5", [FeatureMips64r5]>;
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def : Proc<"mips64r6", [FeatureMips64r6]>;
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def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
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def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
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def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
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def MipsAsmParser : AsmParser {
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let ShouldEmitMatchRegisterName = 0;
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}
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def MipsAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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// Recognize hard coded registers.
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string RegisterPrefix = "$";
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}
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def MipsAsmWriter : AsmWriter {
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int PassSubtarget = 1;
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}
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def Mips : Target {
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let InstructionSet = MipsInstrInfo;
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let AssemblyWriters = [MipsAsmWriter];
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let AssemblyParsers = [MipsAsmParser];
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let AssemblyParserVariants = [MipsAsmParserVariant];
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let AllowRegisterRenaming = 1;
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}
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//===----------------------------------------------------------------------===//
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// Pfm Counters
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//===----------------------------------------------------------------------===//
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include "MipsPfmCounters.td"
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