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01a7967447
The term "next stack offset" is misleading because the next argument is not necessarily allocated at this offset due to alignment constrains. It also does not make much sense when allocating arguments at negative offsets (introduced in a follow-up patch), because the returned offset would be past the end of the next argument. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D149566
577 lines
20 KiB
C++
577 lines
20 KiB
C++
//===- MipsCallLowering.cpp -------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsCallLowering.h"
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#include "MipsCCState.h"
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#include "MipsMachineFunction.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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using namespace llvm;
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MipsCallLowering::MipsCallLowering(const MipsTargetLowering &TLI)
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: CallLowering(&TLI) {}
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namespace {
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struct MipsOutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
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/// This is the name of the function being called
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/// FIXME: Relying on this is unsound
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const char *Func = nullptr;
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/// Is this a return value, or an outgoing call operand.
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bool IsReturn;
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MipsOutgoingValueAssigner(CCAssignFn *AssignFn_, const char *Func,
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bool IsReturn)
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: OutgoingValueAssigner(AssignFn_), Func(Func), IsReturn(IsReturn) {}
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bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
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CCState &State_) override {
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MipsCCState &State = static_cast<MipsCCState &>(State_);
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if (IsReturn)
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State.PreAnalyzeReturnValue(EVT::getEVT(Info.Ty));
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else
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State.PreAnalyzeCallOperand(Info.Ty, Info.IsFixed, Func);
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return CallLowering::OutgoingValueAssigner::assignArg(
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ValNo, OrigVT, ValVT, LocVT, LocInfo, Info, Flags, State);
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}
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};
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struct MipsIncomingValueAssigner : public CallLowering::IncomingValueAssigner {
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/// This is the name of the function being called
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/// FIXME: Relying on this is unsound
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const char *Func = nullptr;
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/// Is this a call return value, or an incoming function argument.
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bool IsReturn;
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MipsIncomingValueAssigner(CCAssignFn *AssignFn_, const char *Func,
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bool IsReturn)
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: IncomingValueAssigner(AssignFn_), Func(Func), IsReturn(IsReturn) {}
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bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
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CCState &State_) override {
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MipsCCState &State = static_cast<MipsCCState &>(State_);
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if (IsReturn)
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State.PreAnalyzeCallResult(Info.Ty, Func);
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else
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State.PreAnalyzeFormalArgument(Info.Ty, Flags);
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return CallLowering::IncomingValueAssigner::assignArg(
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ValNo, OrigVT, ValVT, LocVT, LocInfo, Info, Flags, State);
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}
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};
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class MipsIncomingValueHandler : public CallLowering::IncomingValueHandler {
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const MipsSubtarget &STI;
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public:
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MipsIncomingValueHandler(MachineIRBuilder &MIRBuilder,
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MachineRegisterInfo &MRI)
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: IncomingValueHandler(MIRBuilder, MRI),
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STI(MIRBuilder.getMF().getSubtarget<MipsSubtarget>()) {}
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private:
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void assignValueToReg(Register ValVReg, Register PhysReg,
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CCValAssign VA) override;
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Register getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO,
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ISD::ArgFlagsTy Flags) override;
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void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
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MachinePointerInfo &MPO, CCValAssign &VA) override;
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unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
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ArrayRef<CCValAssign> VAs,
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std::function<void()> *Thunk = nullptr) override;
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virtual void markPhysRegUsed(unsigned PhysReg) {
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MIRBuilder.getMRI()->addLiveIn(PhysReg);
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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}
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};
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class CallReturnHandler : public MipsIncomingValueHandler {
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public:
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CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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MachineInstrBuilder &MIB)
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: MipsIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
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private:
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void markPhysRegUsed(unsigned PhysReg) override {
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MIB.addDef(PhysReg, RegState::Implicit);
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}
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MachineInstrBuilder &MIB;
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};
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} // end anonymous namespace
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void MipsIncomingValueHandler::assignValueToReg(Register ValVReg,
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Register PhysReg,
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CCValAssign VA) {
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markPhysRegUsed(PhysReg);
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IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
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}
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Register MipsIncomingValueHandler::getStackAddress(uint64_t Size,
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int64_t Offset,
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MachinePointerInfo &MPO,
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ISD::ArgFlagsTy Flags) {
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MachineFunction &MF = MIRBuilder.getMF();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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// FIXME: This should only be immutable for non-byval memory arguments.
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int FI = MFI.CreateFixedObject(Size, Offset, true);
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MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
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return MIRBuilder.buildFrameIndex(LLT::pointer(0, 32), FI).getReg(0);
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}
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void MipsIncomingValueHandler::assignValueToAddress(Register ValVReg,
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Register Addr, LLT MemTy,
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MachinePointerInfo &MPO,
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CCValAssign &VA) {
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MachineFunction &MF = MIRBuilder.getMF();
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auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
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inferAlignFromPtrInfo(MF, MPO));
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MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
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}
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/// Handle cases when f64 is split into 2 32-bit GPRs. This is a custom
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/// assignment because generic code assumes getNumRegistersForCallingConv is
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/// accurate. In this case it is not because the type/number are context
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/// dependent on other arguments.
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unsigned
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MipsIncomingValueHandler::assignCustomValue(CallLowering::ArgInfo &Arg,
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ArrayRef<CCValAssign> VAs,
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std::function<void()> *Thunk) {
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const CCValAssign &VALo = VAs[0];
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const CCValAssign &VAHi = VAs[1];
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assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
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VALo.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
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"unexpected custom value");
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auto CopyLo = MIRBuilder.buildCopy(LLT::scalar(32), VALo.getLocReg());
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auto CopyHi = MIRBuilder.buildCopy(LLT::scalar(32), VAHi.getLocReg());
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if (!STI.isLittle())
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std::swap(CopyLo, CopyHi);
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Arg.OrigRegs.assign(Arg.Regs.begin(), Arg.Regs.end());
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Arg.Regs = { CopyLo.getReg(0), CopyHi.getReg(0) };
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MIRBuilder.buildMergeLikeInstr(Arg.OrigRegs[0], {CopyLo, CopyHi});
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markPhysRegUsed(VALo.getLocReg());
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markPhysRegUsed(VAHi.getLocReg());
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return 2;
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}
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namespace {
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class MipsOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
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const MipsSubtarget &STI;
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public:
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MipsOutgoingValueHandler(MachineIRBuilder &MIRBuilder,
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MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)
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: OutgoingValueHandler(MIRBuilder, MRI),
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STI(MIRBuilder.getMF().getSubtarget<MipsSubtarget>()), MIB(MIB) {}
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private:
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void assignValueToReg(Register ValVReg, Register PhysReg,
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CCValAssign VA) override;
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Register getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO,
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ISD::ArgFlagsTy Flags) override;
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void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
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MachinePointerInfo &MPO, CCValAssign &VA) override;
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unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
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ArrayRef<CCValAssign> VAs,
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std::function<void()> *Thunk) override;
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MachineInstrBuilder &MIB;
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};
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} // end anonymous namespace
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void MipsOutgoingValueHandler::assignValueToReg(Register ValVReg,
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Register PhysReg,
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CCValAssign VA) {
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Register ExtReg = extendRegister(ValVReg, VA);
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MIRBuilder.buildCopy(PhysReg, ExtReg);
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MIB.addUse(PhysReg, RegState::Implicit);
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}
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Register MipsOutgoingValueHandler::getStackAddress(uint64_t Size,
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int64_t Offset,
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MachinePointerInfo &MPO,
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ISD::ArgFlagsTy Flags) {
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MachineFunction &MF = MIRBuilder.getMF();
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MPO = MachinePointerInfo::getStack(MF, Offset);
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LLT p0 = LLT::pointer(0, 32);
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LLT s32 = LLT::scalar(32);
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auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP));
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auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
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auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
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return AddrReg.getReg(0);
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}
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void MipsOutgoingValueHandler::assignValueToAddress(Register ValVReg,
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Register Addr, LLT MemTy,
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MachinePointerInfo &MPO,
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CCValAssign &VA) {
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MachineFunction &MF = MIRBuilder.getMF();
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uint64_t LocMemOffset = VA.getLocMemOffset();
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auto MMO = MF.getMachineMemOperand(
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MPO, MachineMemOperand::MOStore, MemTy,
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commonAlignment(STI.getStackAlignment(), LocMemOffset));
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Register ExtReg = extendRegister(ValVReg, VA);
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MIRBuilder.buildStore(ExtReg, Addr, *MMO);
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}
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unsigned
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MipsOutgoingValueHandler::assignCustomValue(CallLowering::ArgInfo &Arg,
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ArrayRef<CCValAssign> VAs,
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std::function<void()> *Thunk) {
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const CCValAssign &VALo = VAs[0];
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const CCValAssign &VAHi = VAs[1];
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assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
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VALo.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
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"unexpected custom value");
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auto Unmerge =
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MIRBuilder.buildUnmerge({LLT::scalar(32), LLT::scalar(32)}, Arg.Regs[0]);
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Register Lo = Unmerge.getReg(0);
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Register Hi = Unmerge.getReg(1);
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Arg.OrigRegs.assign(Arg.Regs.begin(), Arg.Regs.end());
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Arg.Regs = { Lo, Hi };
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if (!STI.isLittle())
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std::swap(Lo, Hi);
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// If we can return a thunk, just include the register copies. The unmerge can
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// be emitted earlier.
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if (Thunk) {
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*Thunk = [=]() {
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MIRBuilder.buildCopy(VALo.getLocReg(), Lo);
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MIRBuilder.buildCopy(VAHi.getLocReg(), Hi);
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};
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return 2;
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}
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MIRBuilder.buildCopy(VALo.getLocReg(), Lo);
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MIRBuilder.buildCopy(VAHi.getLocReg(), Hi);
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return 2;
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}
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static bool isSupportedArgumentType(Type *T) {
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if (T->isIntegerTy())
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return true;
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if (T->isPointerTy())
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return true;
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if (T->isFloatingPointTy())
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return true;
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return false;
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}
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static bool isSupportedReturnType(Type *T) {
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if (T->isIntegerTy())
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return true;
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if (T->isPointerTy())
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return true;
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if (T->isFloatingPointTy())
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return true;
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if (T->isAggregateType())
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return true;
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return false;
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}
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bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, ArrayRef<Register> VRegs,
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FunctionLoweringInfo &FLI) const {
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MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
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if (Val != nullptr && !isSupportedReturnType(Val->getType()))
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return false;
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if (!VRegs.empty()) {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = MF.getFunction();
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const DataLayout &DL = MF.getDataLayout();
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const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
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SmallVector<ArgInfo, 8> RetInfos;
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ArgInfo ArgRetInfo(VRegs, *Val, 0);
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setArgFlags(ArgRetInfo, AttributeList::ReturnIndex, DL, F);
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splitToValueTypes(ArgRetInfo, RetInfos, DL, F.getCallingConv());
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SmallVector<CCValAssign, 16> ArgLocs;
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SmallVector<ISD::OutputArg, 8> Outs;
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MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
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F.getContext());
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MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
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std::string FuncName = F.getName().str();
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MipsOutgoingValueAssigner Assigner(TLI.CCAssignFnForReturn(),
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FuncName.c_str(), /*IsReturn*/ true);
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if (!determineAssignments(Assigner, RetInfos, CCInfo))
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return false;
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if (!handleAssignments(RetHandler, RetInfos, CCInfo, ArgLocs, MIRBuilder))
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return false;
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}
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MIRBuilder.insertInstr(Ret);
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return true;
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}
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bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs,
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FunctionLoweringInfo &FLI) const {
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// Quick exit if there aren't any args.
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if (F.arg_empty())
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return true;
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for (auto &Arg : F.args()) {
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if (!isSupportedArgumentType(Arg.getType()))
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return false;
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}
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MachineFunction &MF = MIRBuilder.getMF();
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const DataLayout &DL = MF.getDataLayout();
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const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
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SmallVector<ArgInfo, 8> ArgInfos;
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unsigned i = 0;
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for (auto &Arg : F.args()) {
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ArgInfo AInfo(VRegs[i], Arg, i);
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setArgFlags(AInfo, i + AttributeList::FirstArgIndex, DL, F);
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splitToValueTypes(AInfo, ArgInfos, DL, F.getCallingConv());
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++i;
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}
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SmallVector<ISD::InputArg, 8> Ins;
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SmallVector<CCValAssign, 16> ArgLocs;
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MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
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F.getContext());
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const MipsTargetMachine &TM =
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static_cast<const MipsTargetMachine &>(MF.getTarget());
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const MipsABIInfo &ABI = TM.getABI();
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CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()),
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Align(1));
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const std::string FuncName = F.getName().str();
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MipsIncomingValueAssigner Assigner(TLI.CCAssignFnForCall(), FuncName.c_str(),
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/*IsReturn*/ false);
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if (!determineAssignments(Assigner, ArgInfos, CCInfo))
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return false;
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MipsIncomingValueHandler Handler(MIRBuilder, MF.getRegInfo());
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if (!handleAssignments(Handler, ArgInfos, CCInfo, ArgLocs, MIRBuilder))
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return false;
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if (F.isVarArg()) {
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ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
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unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
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int VaArgOffset;
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unsigned RegSize = 4;
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if (ArgRegs.size() == Idx)
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VaArgOffset = alignTo(CCInfo.getStackSize(), RegSize);
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else {
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VaArgOffset =
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(int)ABI.GetCalleeAllocdArgSizeInBytes(CCInfo.getCallingConv()) -
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(int)(RegSize * (ArgRegs.size() - Idx));
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}
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MachineFrameInfo &MFI = MF.getFrameInfo();
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int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
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MF.getInfo<MipsFunctionInfo>()->setVarArgsFrameIndex(FI);
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for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) {
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MIRBuilder.getMBB().addLiveIn(ArgRegs[I]);
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LLT RegTy = LLT::scalar(RegSize * 8);
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MachineInstrBuilder Copy =
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MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I]));
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FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
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MachinePointerInfo MPO = MachinePointerInfo::getFixedStack(MF, FI);
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const LLT PtrTy = LLT::pointer(MPO.getAddrSpace(), 32);
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auto FrameIndex = MIRBuilder.buildFrameIndex(PtrTy, FI);
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MPO, MachineMemOperand::MOStore, RegTy, Align(RegSize));
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MIRBuilder.buildStore(Copy, FrameIndex, *MMO);
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}
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}
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return true;
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}
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bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info) const {
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if (Info.CallConv != CallingConv::C)
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return false;
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for (auto &Arg : Info.OrigArgs) {
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if (!isSupportedArgumentType(Arg.Ty))
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return false;
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if (Arg.Flags[0].isByVal())
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return false;
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if (Arg.Flags[0].isSRet() && !Arg.Ty->isPointerTy())
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return false;
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}
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if (!Info.OrigRet.Ty->isVoidTy() && !isSupportedReturnType(Info.OrigRet.Ty))
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return false;
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = MF.getFunction();
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const DataLayout &DL = MF.getDataLayout();
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const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
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const MipsTargetMachine &TM =
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static_cast<const MipsTargetMachine &>(MF.getTarget());
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const MipsABIInfo &ABI = TM.getABI();
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MachineInstrBuilder CallSeqStart =
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MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
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const bool IsCalleeGlobalPIC =
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|
Info.Callee.isGlobal() && TM.isPositionIndependent();
|
|
|
|
MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(
|
|
Info.Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL);
|
|
MIB.addDef(Mips::SP, RegState::Implicit);
|
|
if (IsCalleeGlobalPIC) {
|
|
Register CalleeReg =
|
|
MF.getRegInfo().createGenericVirtualRegister(LLT::pointer(0, 32));
|
|
MachineInstr *CalleeGlobalValue =
|
|
MIRBuilder.buildGlobalValue(CalleeReg, Info.Callee.getGlobal());
|
|
if (!Info.Callee.getGlobal()->hasLocalLinkage())
|
|
CalleeGlobalValue->getOperand(1).setTargetFlags(MipsII::MO_GOT_CALL);
|
|
MIB.addUse(CalleeReg);
|
|
} else
|
|
MIB.add(Info.Callee);
|
|
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
|
MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
|
|
|
|
TargetLowering::ArgListTy FuncOrigArgs;
|
|
FuncOrigArgs.reserve(Info.OrigArgs.size());
|
|
|
|
SmallVector<ArgInfo, 8> ArgInfos;
|
|
for (auto &Arg : Info.OrigArgs)
|
|
splitToValueTypes(Arg, ArgInfos, DL, Info.CallConv);
|
|
|
|
SmallVector<CCValAssign, 8> ArgLocs;
|
|
bool IsCalleeVarArg = false;
|
|
if (Info.Callee.isGlobal()) {
|
|
const Function *CF = static_cast<const Function *>(Info.Callee.getGlobal());
|
|
IsCalleeVarArg = CF->isVarArg();
|
|
}
|
|
|
|
// FIXME: Should use MipsCCState::getSpecialCallingConvForCallee, but it
|
|
// depends on looking directly at the call target.
|
|
MipsCCState CCInfo(Info.CallConv, IsCalleeVarArg, MF, ArgLocs,
|
|
F.getContext());
|
|
|
|
CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(Info.CallConv),
|
|
Align(1));
|
|
|
|
const char *Call =
|
|
Info.Callee.isSymbol() ? Info.Callee.getSymbolName() : nullptr;
|
|
|
|
MipsOutgoingValueAssigner Assigner(TLI.CCAssignFnForCall(), Call,
|
|
/*IsReturn*/ false);
|
|
if (!determineAssignments(Assigner, ArgInfos, CCInfo))
|
|
return false;
|
|
|
|
MipsOutgoingValueHandler ArgHandler(MIRBuilder, MF.getRegInfo(), MIB);
|
|
if (!handleAssignments(ArgHandler, ArgInfos, CCInfo, ArgLocs, MIRBuilder))
|
|
return false;
|
|
|
|
unsigned StackSize = CCInfo.getStackSize();
|
|
unsigned StackAlignment = F.getParent()->getOverrideStackAlignment();
|
|
if (!StackAlignment) {
|
|
const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
|
|
StackAlignment = TFL->getStackAlignment();
|
|
}
|
|
StackSize = alignTo(StackSize, StackAlignment);
|
|
CallSeqStart.addImm(StackSize).addImm(0);
|
|
|
|
if (IsCalleeGlobalPIC) {
|
|
MIRBuilder.buildCopy(
|
|
Register(Mips::GP),
|
|
MF.getInfo<MipsFunctionInfo>()->getGlobalBaseRegForGlobalISel(MF));
|
|
MIB.addDef(Mips::GP, RegState::Implicit);
|
|
}
|
|
MIRBuilder.insertInstr(MIB);
|
|
if (MIB->getOpcode() == Mips::JALRPseudo) {
|
|
const MipsSubtarget &STI = MIRBuilder.getMF().getSubtarget<MipsSubtarget>();
|
|
MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
|
|
*STI.getRegBankInfo());
|
|
}
|
|
|
|
if (!Info.OrigRet.Ty->isVoidTy()) {
|
|
ArgInfos.clear();
|
|
|
|
CallLowering::splitToValueTypes(Info.OrigRet, ArgInfos, DL,
|
|
F.getCallingConv());
|
|
|
|
const std::string FuncName = F.getName().str();
|
|
SmallVector<ISD::InputArg, 8> Ins;
|
|
SmallVector<CCValAssign, 8> ArgLocs;
|
|
MipsIncomingValueAssigner Assigner(TLI.CCAssignFnForReturn(),
|
|
FuncName.c_str(),
|
|
/*IsReturn*/ true);
|
|
CallReturnHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
|
|
|
|
MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
|
|
F.getContext());
|
|
|
|
if (!determineAssignments(Assigner, ArgInfos, CCInfo))
|
|
return false;
|
|
|
|
if (!handleAssignments(RetHandler, ArgInfos, CCInfo, ArgLocs, MIRBuilder))
|
|
return false;
|
|
}
|
|
|
|
MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(StackSize).addImm(0);
|
|
|
|
return true;
|
|
}
|