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d768d35515
This patch adds a new ReadAdvance definition named ReadInt2Fpu. ReadInt2Fpu allows x86 scheduling models to accurately describe delays caused by data transfers from the integer unit to the floating point unit. ReadInt2Fpu currently defaults to a delay of zero cycles (i.e. no delay) for all x86 models excluding BtVer2. That means, this patch is only a functional change for the Jaguar cpu model only. Tablegen definitions for instructions (V)PINSR* have been updated to account for the new ReadInt2Fpu. That read is mapped to the the GPR input operand. On Jaguar, int-to-fpu transfers are modeled as a +6cy delay. Before this patch, that extra delay was added to the opcode latency. In practice, the insert opcode only executes for 1cy. Most of the actual latency is actually contributed by the so-called operand-latency. According to the AMD SOG for family 16h, (V)PINSR* latency is defined by expression f+1, where f is defined as a forwarding delay from the integer unit to the fpu. When printing instruction latency from MCA (see InstructionInfoView.cpp) and LLC (only when flag -print-schedule is speified), we now need to account for any extra forwarding delays. We do this by checking if scheduling classes declare any negative ReadAdvance entries. Quoting a code comment in TargetSchedule.td: "A negative advance effectively increases latency, which may be used for cross-domain stalls". When computing the instruction latency for the purpose of our scheduling tests, we now add any extra delay to the formula. This avoids regressing existing codegen and mca schedule tests. It comes with the cost of an extra (but very simple) hook in MCSchedModel. Differential Revision: https://reviews.llvm.org/D57056 llvm-svn: 351965
130 lines
4.4 KiB
C++
130 lines
4.4 KiB
C++
//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file describes the general parts of a Subtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/raw_ostream.h"
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#include <string>
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using namespace llvm;
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TargetSubtargetInfo::TargetSubtargetInfo(
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const Triple &TT, StringRef CPU, StringRef FS,
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ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
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const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
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const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
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const InstrStage *IS, const unsigned *OC, const unsigned *FP)
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: MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
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}
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TargetSubtargetInfo::~TargetSubtargetInfo() = default;
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bool TargetSubtargetInfo::enableAtomicExpand() const {
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return true;
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}
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bool TargetSubtargetInfo::enableIndirectBrExpand() const {
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return false;
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}
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bool TargetSubtargetInfo::enableMachineScheduler() const {
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return false;
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}
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bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
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return enableMachineScheduler();
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}
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bool TargetSubtargetInfo::enableRALocalReassignment(
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CodeGenOpt::Level OptLevel) const {
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return true;
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}
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bool TargetSubtargetInfo::enableAdvancedRASplitCost() const {
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return false;
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}
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bool TargetSubtargetInfo::enablePostRAScheduler() const {
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return getSchedModel().PostRAScheduler;
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}
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bool TargetSubtargetInfo::useAA() const {
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return false;
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}
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static std::string createSchedInfoStr(unsigned Latency, double RThroughput) {
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static const char *SchedPrefix = " sched: [";
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std::string Comment;
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raw_string_ostream CS(Comment);
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if (RThroughput != 0.0)
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CS << SchedPrefix << Latency << format(":%2.2f", RThroughput)
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<< "]";
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else
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CS << SchedPrefix << Latency << ":?]";
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CS.flush();
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return Comment;
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}
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/// Returns string representation of scheduler comment
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std::string TargetSubtargetInfo::getSchedInfoStr(const MachineInstr &MI) const {
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if (MI.isPseudo() || MI.isTerminator())
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return std::string();
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// We don't cache TSchedModel because it depends on TargetInstrInfo
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// that could be changed during the compilation
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TargetSchedModel TSchedModel;
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TSchedModel.init(this);
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unsigned Latency = TSchedModel.computeInstrLatency(&MI);
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// Add extra latency due to forwarding delays.
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const MCSchedClassDesc &SCDesc = *TSchedModel.resolveSchedClass(&MI);
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Latency +=
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MCSchedModel::getForwardingDelayCycles(getReadAdvanceEntries(SCDesc));
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double RThroughput = TSchedModel.computeReciprocalThroughput(&MI);
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return createSchedInfoStr(Latency, RThroughput);
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}
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/// Returns string representation of scheduler comment
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std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
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// We don't cache TSchedModel because it depends on TargetInstrInfo
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// that could be changed during the compilation
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TargetSchedModel TSchedModel;
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TSchedModel.init(this);
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unsigned Latency;
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if (TSchedModel.hasInstrSchedModel()) {
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Latency = TSchedModel.computeInstrLatency(MCI);
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// Add extra latency due to forwarding delays.
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const MCSchedModel &SM = *TSchedModel.getMCSchedModel();
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unsigned SClassID = getInstrInfo()->get(MCI.getOpcode()).getSchedClass();
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while (SM.getSchedClassDesc(SClassID)->isVariant())
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SClassID = resolveVariantSchedClass(SClassID, &MCI, SM.ProcID);
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const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SClassID);
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Latency +=
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MCSchedModel::getForwardingDelayCycles(getReadAdvanceEntries(SCDesc));
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} else if (TSchedModel.hasInstrItineraries()) {
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auto *ItinData = TSchedModel.getInstrItineraries();
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Latency = ItinData->getStageLatency(
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getInstrInfo()->get(MCI.getOpcode()).getSchedClass());
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} else
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return std::string();
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double RThroughput = TSchedModel.computeReciprocalThroughput(MCI);
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return createSchedInfoStr(Latency, RThroughput);
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}
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void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const {
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}
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