Sanjay Patel 70c5f02d25 [DAG] disable nsw/nuw for add/sub/mul when simplifying based on demanded bits (PR30841) ...

This bug was exposed by using nsw/nuw for more aggressive folds in:
https://reviews.llvm.org/rL284844

The changes mimic the IR demanded bits logic in InstCombiner::SimplifyDemandedUseBits(),
but we can't just flip flag bits in the DAG; we have to create a new node that has the
bits cleared.

This should fix:
https://llvm.org/bugs/show_bug.cgi?id=30841 

llvm-svn: 285656

2016-10-31 23:28:45 +00:00

..

CMakeLists.txt

Rename TargetSelectionDAGInfo into SelectionDAGTargetInfo and move it to CodeGen/

2016-01-27 16:32:26 +00:00

DAGCombiner.cpp

[DAG] x | x --> x

2016-10-30 18:19:35 +00:00

FastISel.cpp

swifterror: Don't compute swifterror vregs during instruction selection

2016-10-07 22:06:55 +00:00

FunctionLoweringInfo.cpp

[WinEH] Allow catchpads to reuse the same catch object

2016-10-19 17:08:23 +00:00

InstrEmitter.cpp

SDAG: Make sure we use an allocatable reg class when we create this vreg

2016-10-28 22:42:54 +00:00

InstrEmitter.h

Pass DebugLoc and SDLoc by const ref.

2016-06-12 15:39:02 +00:00

LegalizeDAG.cpp

LegalizeDAG: Support promoting [US]DIV and [US]REM operations

2016-10-26 14:52:25 +00:00

LegalizeFloatTypes.cpp

[CodeGen] Split out the notions of MI invariance and MI dereferenceability.

2016-09-11 01:38:58 +00:00

LegalizeIntegerTypes.cpp

Fix *_EXTEND_VECTOR_INREG legalization

2016-10-20 17:56:36 +00:00

LegalizeTypes.cpp

getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits(), round 2 ; NFCI

2016-09-14 16:54:10 +00:00

LegalizeTypes.h

[SelectionDAGBuilder] Support llvm.flt.rounds on targets where i32 is not legal

2016-10-10 20:45:15 +00:00

LegalizeTypesGeneric.cpp

Do not assume that FP vector operands are never legalized by expanding

2016-10-26 19:51:35 +00:00

LegalizeVectorOps.cpp

getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCI

2016-09-14 16:37:15 +00:00

LegalizeVectorTypes.cpp

getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCI

2016-09-14 16:37:15 +00:00

LLVMBuild.txt

…

ResourcePriorityQueue.cpp

Use the range variant of find instead of unpacking begin/end

2016-08-11 22:21:41 +00:00

ScheduleDAGFast.cpp

…

ScheduleDAGRRList.cpp

Use the range variant of find instead of unpacking begin/end

2016-08-11 22:21:41 +00:00

ScheduleDAGSDNodes.cpp

SelectionDAG: Avoid implicit iterator conversions in ScheduleDAGSDNodes, NFC

2016-07-08 19:07:09 +00:00

ScheduleDAGSDNodes.h

…

ScheduleDAGVLIW.cpp

…

SDNodeDbgValue.h

Apply clang-tidy's misc-move-constructor-init throughout LLVM.

2016-05-27 14:27:24 +00:00

SelectionDAG.cpp

[DAGCombiner] (REAPPLIED) Add vector demanded elements support to computeKnownBits

2016-10-29 11:29:39 +00:00

SelectionDAGBuilder.cpp

Switch lowering: improve partitioning of jump tables

2016-10-25 19:11:43 +00:00

SelectionDAGBuilder.h

Delete some dead code in SelectionDAG (NFC)

2016-10-06 22:53:43 +00:00

SelectionDAGDumper.cpp

Create llvm.addressofreturnaddress intrinsic

2016-10-12 22:13:19 +00:00

SelectionDAGISel.cpp

Silence -Wunused-but-set-variable warning

2016-10-11 19:49:29 +00:00

SelectionDAGPrinter.cpp

…

SelectionDAGTargetInfo.cpp

Rename TargetSelectionDAGInfo into SelectionDAGTargetInfo and move it to CodeGen/

2016-01-27 16:32:26 +00:00

StatepointLowering.cpp

getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCI

2016-09-14 16:05:51 +00:00

StatepointLowering.h

[NFC] Header cleanup

2016-04-18 09:17:29 +00:00

TargetLowering.cpp

[DAG] disable nsw/nuw for add/sub/mul when simplifying based on demanded bits (PR30841)

2016-10-31 23:28:45 +00:00