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llvm-project/llvm/lib/CodeGen/SelectionDAG
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Simon Pilgrim 2b3b453a82 [TargetLowering] Only demand a funnelshift's modulo amount bits 
ISD::FSHL/FSHR shift amount values are guaranteed to act as a modulo amount, so for power-of-2 bitwidths we only need the lowest bits.
2020-03-16 13:52:17 +00:00
..
CMakeLists.txt
[cmake] Explicitly mark libraries defined in lib/ as "Component Libraries"
2019-11-21 10:48:08 -08:00
DAGCombiner.cpp
[DAG] MatchRotate - Add funnel shift by variable support
2020-03-15 11:50:45 +00:00
FastISel.cpp
Add dbgs() output to help track down missing DW_AT_location bugs, NFC
2020-02-13 14:38:44 -08:00
FunctionLoweringInfo.cpp
[KnownBits] Introduce anyext instead of passing a flag into zext
2020-02-12 19:06:53 +00:00
InstrEmitter.cpp
Reland "[WebAssembly][InstrEmitter] Foundation for multivalue call lowering"
2020-02-18 13:49:46 -08:00
InstrEmitter.h
…
LegalizeDAG.cpp
No longer generate calls to *_finite
2020-02-28 10:07:37 +01:00
LegalizeFloatTypes.cpp
[X86][LegalizeTypes] Add SoftPromoteHalf support STRICT_FP_EXTEND and STRICT_FP_ROUND
2020-02-11 22:30:04 -08:00
LegalizeIntegerTypes.cpp
[SelectionDAG][PowerPC][AArch64][X86][ARM] Add chain input and output the ISD::FLT_ROUNDS_
2020-02-25 16:58:23 -08:00
LegalizeTypes.cpp
[LegalizeTypes][ARM][AArch64][PowerPC][RISCV][X86] Use BUILD_PAIR to return expanded integer results from ReplaceNodeResults instead of just returning two results.
2020-02-08 09:52:31 -08:00
LegalizeTypes.h
[LegalizeTypes][X86] Add a new strategy for type legalizing f16 type that softens it to i16, but promotes to f32 around arithmetic ops.
2020-02-01 11:21:04 -08:00
LegalizeTypesGeneric.cpp
[LegalizeTypes][X86] Add a new strategy for type legalizing f16 type that softens it to i16, but promotes to f32 around arithmetic ops.
2020-02-01 11:21:04 -08:00
LegalizeVectorOps.cpp
[SDAG] Add SDNode::values() = make_range(values_begin(), values_end())
2020-02-26 12:07:38 -06:00
LegalizeVectorTypes.cpp
[LegalizeTypes] Scalarize non-byte sized loads in WidenRecRes_Load and SplitVecResLoad
2020-02-24 15:14:33 -08:00
LLVMBuild.txt
…
ResourcePriorityQueue.cpp
…
ScheduleDAGFast.cpp
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
2019-08-01 23:27:28 +00:00
ScheduleDAGRRList.cpp
[ScheduleDAG] When a node is cloned, add an edge between the nodes.
2019-10-04 19:51:40 +00:00
ScheduleDAGSDNodes.cpp
[CallSiteInfo] Enable the call site info only for -g + optimizations
2020-03-09 12:12:44 +01:00
ScheduleDAGSDNodes.h
Prune Analysis includes from SelectionDAG.h
2019-10-19 01:07:48 +00:00
ScheduleDAGVLIW.cpp
Prune Analysis includes from SelectionDAG.h
2019-10-19 01:07:48 +00:00
SDNodeDbgValue.h
…
SelectionDAG.cpp
[WebAssembly] Fix SIMD shift unrolling to avoid assertion failure
2020-03-12 12:20:14 -07:00
SelectionDAGAddressAnalysis.cpp
Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each
2019-10-19 01:31:09 +00:00
SelectionDAGBuilder.cpp
[SelectionDAGBuilder] Simplify the struct type handling in getUniformBase.
2020-03-13 14:00:21 -07:00
SelectionDAGBuilder.h
[FPEnv] Fix chain handling regression after 04a8696
2020-01-14 14:10:57 +01:00
SelectionDAGDumper.cpp
[Intrinsic] Add fixed point saturating division intrinsics.
2020-02-24 10:50:52 +01:00
SelectionDAGISel.cpp
Add dbgs() output to help track down missing DW_AT_location bugs, NFC
2020-02-13 14:38:44 -08:00
SelectionDAGPrinter.cpp
Make llvm::StringRef to std::string conversions explicit.
2020-01-28 23:25:25 +01:00
SelectionDAGTargetInfo.cpp
…
StatepointLowering.cpp
Remove unused variable.
2020-03-12 08:42:57 +01:00
StatepointLowering.h
…
TargetLowering.cpp
[TargetLowering] Only demand a funnelshift's modulo amount bits
2020-03-16 13:52:17 +00:00