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117e952a53
When LiveRangeEdit::eliminateDeadDef() converts an MI to a KILL instruction, it should also call dropMemRefs() in order to erase any MachineMemOperand present. This was discovered in testing as the MachineVerifier does not accept an MMO without the corresponding MI mayLoad/mayStore flag, which the KILL opcode lacks.
510 lines
18 KiB
C++
510 lines
18 KiB
C++
//===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The LiveRangeEdit class represents changes done to a virtual register when it
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// is spilled or split.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveRangeEdit.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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STATISTIC(NumDCEDeleted, "Number of instructions deleted by DCE");
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STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE");
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STATISTIC(NumFracRanges, "Number of live ranges fractured by DCE");
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STATISTIC(NumReMaterialization, "Number of instructions rematerialized");
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void LiveRangeEdit::Delegate::anchor() { }
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LiveInterval &LiveRangeEdit::createEmptyIntervalFrom(Register OldReg,
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bool createSubRanges) {
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Register VReg = MRI.cloneVirtualRegister(OldReg);
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if (VRM)
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VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
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LiveInterval &LI = LIS.createEmptyInterval(VReg);
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if (Parent && !Parent->isSpillable())
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LI.markNotSpillable();
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if (createSubRanges) {
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// Create empty subranges if the OldReg's interval has them. Do not create
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// the main range here---it will be constructed later after the subranges
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// have been finalized.
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LiveInterval &OldLI = LIS.getInterval(OldReg);
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VNInfo::Allocator &Alloc = LIS.getVNInfoAllocator();
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for (LiveInterval::SubRange &S : OldLI.subranges())
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LI.createSubRange(Alloc, S.LaneMask);
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}
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return LI;
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}
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Register LiveRangeEdit::createFrom(Register OldReg) {
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Register VReg = MRI.cloneVirtualRegister(OldReg);
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if (VRM) {
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VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
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}
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// FIXME: Getting the interval here actually computes it.
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// In theory, this may not be what we want, but in practice
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// the createEmptyIntervalFrom API is used when this is not
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// the case. Generally speaking we just want to annotate the
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// LiveInterval when it gets created but we cannot do that at
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// the moment.
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if (Parent && !Parent->isSpillable())
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LIS.getInterval(VReg).markNotSpillable();
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return VReg;
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}
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bool LiveRangeEdit::checkRematerializable(VNInfo *VNI,
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const MachineInstr *DefMI) {
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assert(DefMI && "Missing instruction");
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ScannedRemattable = true;
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if (!TII.isTriviallyReMaterializable(*DefMI))
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return false;
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Remattable.insert(VNI);
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return true;
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}
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void LiveRangeEdit::scanRemattable() {
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for (VNInfo *VNI : getParent().valnos) {
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if (VNI->isUnused())
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continue;
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Register Original = VRM->getOriginal(getReg());
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LiveInterval &OrigLI = LIS.getInterval(Original);
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VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
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if (!OrigVNI)
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continue;
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MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def);
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if (!DefMI)
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continue;
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checkRematerializable(OrigVNI, DefMI);
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}
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ScannedRemattable = true;
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}
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bool LiveRangeEdit::anyRematerializable() {
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if (!ScannedRemattable)
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scanRemattable();
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return !Remattable.empty();
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}
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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/// OrigIdx are also available with the same value at UseIdx.
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bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
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SlotIndex OrigIdx,
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SlotIndex UseIdx) const {
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OrigIdx = OrigIdx.getRegSlot(true);
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UseIdx = std::max(UseIdx, UseIdx.getRegSlot(true));
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for (const MachineOperand &MO : OrigMI->operands()) {
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if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
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continue;
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// We can't remat physreg uses, unless it is a constant or target wants
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// to ignore this use.
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if (MO.getReg().isPhysical()) {
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if (MRI.isConstantPhysReg(MO.getReg()) || TII.isIgnorableUse(MO))
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continue;
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return false;
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}
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LiveInterval &li = LIS.getInterval(MO.getReg());
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const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
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if (!OVNI)
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continue;
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// Don't allow rematerialization immediately after the original def.
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// It would be incorrect if OrigMI redefines the register.
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// See PR14098.
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if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
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return false;
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if (OVNI != li.getVNInfoAt(UseIdx))
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return false;
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// Check that subrange is live at UseIdx.
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if (li.hasSubRanges()) {
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const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
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unsigned SubReg = MO.getSubReg();
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LaneBitmask LM = SubReg ? TRI->getSubRegIndexLaneMask(SubReg)
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: MRI.getMaxLaneMaskForVReg(MO.getReg());
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for (LiveInterval::SubRange &SR : li.subranges()) {
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if ((SR.LaneMask & LM).none())
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continue;
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if (!SR.liveAt(UseIdx))
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return false;
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// Early exit if all used lanes are checked. No need to continue.
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LM &= ~SR.LaneMask;
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if (LM.none())
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break;
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}
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}
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}
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return true;
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}
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bool LiveRangeEdit::canRematerializeAt(Remat &RM, VNInfo *OrigVNI,
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SlotIndex UseIdx, bool cheapAsAMove) {
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assert(ScannedRemattable && "Call anyRematerializable first");
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// Use scanRemattable info.
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if (!Remattable.count(OrigVNI))
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return false;
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// No defining instruction provided.
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SlotIndex DefIdx;
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assert(RM.OrigMI && "No defining instruction for remattable value");
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DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
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// If only cheap remats were requested, bail out early.
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if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI))
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return false;
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// Verify that all used registers are available with the same values.
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if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
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return false;
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return true;
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}
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SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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Register DestReg, const Remat &RM,
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const TargetRegisterInfo &tri,
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bool Late, unsigned SubIdx,
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MachineInstr *ReplaceIndexMI) {
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assert(RM.OrigMI && "Invalid remat");
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TII.reMaterialize(MBB, MI, DestReg, SubIdx, *RM.OrigMI, tri);
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// DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
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// to false anyway in case the isDead flag of RM.OrigMI's dest register
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// is true.
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(*--MI).clearRegisterDeads(DestReg);
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Rematted.insert(RM.ParentVNI);
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++NumReMaterialization;
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if (ReplaceIndexMI)
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return LIS.ReplaceMachineInstrInMaps(*ReplaceIndexMI, *MI).getRegSlot();
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return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot();
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}
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void LiveRangeEdit::eraseVirtReg(Register Reg) {
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if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
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LIS.removeInterval(Reg);
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}
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bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
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SmallVectorImpl<MachineInstr*> &Dead) {
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MachineInstr *DefMI = nullptr, *UseMI = nullptr;
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// Check that there is a single def and a single use.
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for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg())) {
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MachineInstr *MI = MO.getParent();
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if (MO.isDef()) {
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if (DefMI && DefMI != MI)
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return false;
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if (!MI->canFoldAsLoad())
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return false;
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DefMI = MI;
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} else if (!MO.isUndef()) {
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if (UseMI && UseMI != MI)
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return false;
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// FIXME: Targets don't know how to fold subreg uses.
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if (MO.getSubReg())
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return false;
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UseMI = MI;
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}
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}
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if (!DefMI || !UseMI)
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return false;
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// Since we're moving the DefMI load, make sure we're not extending any live
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// ranges.
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if (!allUsesAvailableAt(DefMI, LIS.getInstructionIndex(*DefMI),
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LIS.getInstructionIndex(*UseMI)))
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return false;
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// We also need to make sure it is safe to move the load.
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// Assume there are stores between DefMI and UseMI.
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bool SawStore = true;
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if (!DefMI->isSafeToMove(SawStore))
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return false;
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LLVM_DEBUG(dbgs() << "Try to fold single def: " << *DefMI
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<< " into single use: " << *UseMI);
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SmallVector<unsigned, 8> Ops;
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if (UseMI->readsWritesVirtualRegister(LI->reg(), &Ops).second)
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return false;
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MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
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if (!FoldMI)
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return false;
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LLVM_DEBUG(dbgs() << " folded: " << *FoldMI);
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LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
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// Update the call site info.
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if (UseMI->shouldUpdateCallSiteInfo())
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UseMI->getMF()->moveCallSiteInfo(UseMI, FoldMI);
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UseMI->eraseFromParent();
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DefMI->addRegisterDead(LI->reg(), nullptr);
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Dead.push_back(DefMI);
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++NumDCEFoldedLoads;
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return true;
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}
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bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
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const MachineOperand &MO) const {
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const MachineInstr &MI = *MO.getParent();
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SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
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if (LI.Query(Idx).isKill())
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return true;
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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unsigned SubReg = MO.getSubReg();
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LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
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for (const LiveInterval::SubRange &S : LI.subranges()) {
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if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
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return true;
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}
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return false;
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}
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/// Find all live intervals that need to shrink, then remove the instruction.
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void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink) {
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assert(MI->allDefsAreDead() && "Def isn't really dead");
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SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
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// Never delete a bundled instruction.
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if (MI->isBundled()) {
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// TODO: Handle deleting copy bundles
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LLVM_DEBUG(dbgs() << "Won't delete dead bundled inst: " << Idx << '\t'
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<< *MI);
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return;
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}
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// Never delete inline asm.
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if (MI->isInlineAsm()) {
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LLVM_DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
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return;
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}
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// Use the same criteria as DeadMachineInstructionElim.
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bool SawStore = false;
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if (!MI->isSafeToMove(SawStore)) {
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LLVM_DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
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return;
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}
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LLVM_DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
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// Collect virtual registers to be erased after MI is gone.
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SmallVector<Register, 8> RegsToErase;
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bool ReadsPhysRegs = false;
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bool isOrigDef = false;
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Register Dest;
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unsigned DestSubReg;
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// Only optimize rematerialize case when the instruction has one def, since
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// otherwise we could leave some dead defs in the code. This case is
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// extremely rare.
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if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
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MI->getDesc().getNumDefs() == 1) {
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Dest = MI->getOperand(0).getReg();
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DestSubReg = MI->getOperand(0).getSubReg();
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Register Original = VRM->getOriginal(Dest);
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LiveInterval &OrigLI = LIS.getInterval(Original);
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VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
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// The original live-range may have been shrunk to
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// an empty live-range. It happens when it is dead, but
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// we still keep it around to be able to rematerialize
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// other values that depend on it.
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if (OrigVNI)
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isOrigDef = SlotIndex::isSameInstr(OrigVNI->def, Idx);
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}
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bool HasLiveVRegUses = false;
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// Check for live intervals that may shrink
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for (const MachineOperand &MO : MI->operands()) {
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if (!MO.isReg())
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continue;
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Register Reg = MO.getReg();
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if (!Reg.isVirtual()) {
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// Check if MI reads any unreserved physregs.
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if (Reg && MO.readsReg() && !MRI.isReserved(Reg))
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ReadsPhysRegs = true;
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else if (MO.isDef())
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LIS.removePhysRegDefAt(Reg.asMCReg(), Idx);
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continue;
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}
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LiveInterval &LI = LIS.getInterval(Reg);
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// Shrink read registers, unless it is likely to be expensive and
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// unlikely to change anything. We typically don't want to shrink the
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// PIC base register that has lots of uses everywhere.
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// Always shrink COPY uses that probably come from live range splitting.
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if ((MI->readsVirtualRegister(Reg) &&
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(MO.isDef() || TII.isCopyInstr(*MI))) ||
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(MO.readsReg() && (MRI.hasOneNonDBGUse(Reg) || useIsKill(LI, MO))))
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ToShrink.insert(&LI);
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else if (MO.readsReg())
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HasLiveVRegUses = true;
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// Remove defined value.
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if (MO.isDef()) {
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if (TheDelegate && LI.getVNInfoAt(Idx) != nullptr)
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TheDelegate->LRE_WillShrinkVirtReg(LI.reg());
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LIS.removeVRegDefAt(LI, Idx);
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if (LI.empty())
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RegsToErase.push_back(Reg);
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}
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}
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// Currently, we don't support DCE of physreg live ranges. If MI reads
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// any unreserved physregs, don't erase the instruction, but turn it into
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// a KILL instead. This way, the physreg live ranges don't end up
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// dangling.
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// FIXME: It would be better to have something like shrinkToUses() for
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// physregs. That could potentially enable more DCE and it would free up
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// the physreg. It would not happen often, though.
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if (ReadsPhysRegs) {
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MI->setDesc(TII.get(TargetOpcode::KILL));
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// Remove all operands that aren't physregs.
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for (unsigned i = MI->getNumOperands(); i; --i) {
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const MachineOperand &MO = MI->getOperand(i-1);
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if (MO.isReg() && MO.getReg().isPhysical())
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continue;
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MI->removeOperand(i-1);
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}
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MI->dropMemRefs(*MI->getMF());
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LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
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} else {
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// If the dest of MI is an original reg and MI is reMaterializable,
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// don't delete the inst. Replace the dest with a new reg, and keep
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// the inst for remat of other siblings. The inst is saved in
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// LiveRangeEdit::DeadRemats and will be deleted after all the
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// allocations of the func are done.
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// However, immediately delete instructions which have unshrunk virtual
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// register uses. That may provoke RA to split an interval at the KILL
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// and later result in an invalid live segment end.
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if (isOrigDef && DeadRemats && !HasLiveVRegUses &&
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TII.isTriviallyReMaterializable(*MI)) {
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LiveInterval &NewLI = createEmptyIntervalFrom(Dest, false);
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VNInfo::Allocator &Alloc = LIS.getVNInfoAllocator();
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VNInfo *VNI = NewLI.getNextValue(Idx, Alloc);
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NewLI.addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(), VNI));
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if (DestSubReg) {
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const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
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auto *SR = NewLI.createSubRange(
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Alloc, TRI->getSubRegIndexLaneMask(DestSubReg));
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SR->addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(),
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SR->getNextValue(Idx, Alloc)));
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}
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pop_back();
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DeadRemats->insert(MI);
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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MI->substituteRegister(Dest, NewLI.reg(), 0, TRI);
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assert(MI->registerDefIsDead(NewLI.reg(), &TRI));
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} else {
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if (TheDelegate)
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TheDelegate->LRE_WillEraseInstruction(MI);
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LIS.RemoveMachineInstrFromMaps(*MI);
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MI->eraseFromParent();
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++NumDCEDeleted;
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}
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}
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// Erase any virtregs that are now empty and unused. There may be <undef>
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// uses around. Keep the empty live range in that case.
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for (Register Reg : RegsToErase) {
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if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) {
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ToShrink.remove(&LIS.getInterval(Reg));
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eraseVirtReg(Reg);
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}
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}
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}
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void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead,
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ArrayRef<Register> RegsBeingSpilled) {
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ToShrinkSet ToShrink;
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for (;;) {
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// Erase all dead defs.
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while (!Dead.empty())
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eliminateDeadDef(Dead.pop_back_val(), ToShrink);
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if (ToShrink.empty())
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break;
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// Shrink just one live interval. Then delete new dead defs.
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LiveInterval *LI = ToShrink.pop_back_val();
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if (foldAsLoad(LI, Dead))
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continue;
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Register VReg = LI->reg();
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if (TheDelegate)
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TheDelegate->LRE_WillShrinkVirtReg(VReg);
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if (!LIS.shrinkToUses(LI, &Dead))
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continue;
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// Don't create new intervals for a register being spilled.
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// The new intervals would have to be spilled anyway so its not worth it.
|
|
// Also they currently aren't spilled so creating them and not spilling
|
|
// them results in incorrect code.
|
|
if (llvm::is_contained(RegsBeingSpilled, VReg))
|
|
continue;
|
|
|
|
// LI may have been separated, create new intervals.
|
|
LI->RenumberValues();
|
|
SmallVector<LiveInterval*, 8> SplitLIs;
|
|
LIS.splitSeparateComponents(*LI, SplitLIs);
|
|
if (!SplitLIs.empty())
|
|
++NumFracRanges;
|
|
|
|
Register Original = VRM ? VRM->getOriginal(VReg) : Register();
|
|
for (const LiveInterval *SplitLI : SplitLIs) {
|
|
// If LI is an original interval that hasn't been split yet, make the new
|
|
// intervals their own originals instead of referring to LI. The original
|
|
// interval must contain all the split products, and LI doesn't.
|
|
if (Original != VReg && Original != 0)
|
|
VRM->setIsSplitFromReg(SplitLI->reg(), Original);
|
|
if (TheDelegate)
|
|
TheDelegate->LRE_DidCloneVirtReg(SplitLI->reg(), VReg);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Keep track of new virtual registers created via
|
|
// MachineRegisterInfo::createVirtualRegister.
|
|
void
|
|
LiveRangeEdit::MRI_NoteNewVirtualRegister(Register VReg) {
|
|
if (VRM)
|
|
VRM->grow();
|
|
|
|
NewRegs.push_back(VReg);
|
|
}
|
|
|
|
void LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
|
|
VirtRegAuxInfo &VRAI) {
|
|
for (unsigned I = 0, Size = size(); I < Size; ++I) {
|
|
LiveInterval &LI = LIS.getInterval(get(I));
|
|
if (MRI.recomputeRegClass(LI.reg()))
|
|
LLVM_DEBUG({
|
|
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
|
dbgs() << "Inflated " << printReg(LI.reg()) << " to "
|
|
<< TRI->getRegClassName(MRI.getRegClass(LI.reg())) << '\n';
|
|
});
|
|
VRAI.calculateSpillWeightAndHint(LI);
|
|
}
|
|
}
|