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94ebd7d9ff
Somehow there was no verification of this, other than an ad-hoc assertion in TwoAddressInstructions.
60 lines
2.3 KiB
YAML
60 lines
2.3 KiB
YAML
# REQUIRES: amdgpu-registered-target
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# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s
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---
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name: invalid_reg_sequence
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tracksRegLiveness: true
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body: |
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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%1:vgpr_32 = IMPLICIT_DEF
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; No operands
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; CHECK: *** Bad machine code: Too few operands ***
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REG_SEQUENCE
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; Only dest operand
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; CHECK: *** Bad machine code: Too few operands ***
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%2:vreg_64 = REG_SEQUENCE
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; Missing destination
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; CHECK: *** Bad machine code: Explicit definition marked as use ***
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REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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; Missing subreg operand
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; CHECK: *** Bad machine code: Invalid number of operands for REG_SEQUENCE ***
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%3:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1
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; Missing register operand
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; CHECK: *** Bad machine code: Invalid number of operands for REG_SEQUENCE ***
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%4:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %subreg.sub1
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; Physreg destination
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; CHECK: *** Bad machine code: REG_SEQUENCE does not support physical register results ***
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$vgpr0_vgpr1 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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; Subreg in destination
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; CHECK: *** Bad machine code: Invalid subreg result for REG_SEQUENCE ***
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%5.sub0_sub1:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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; All operands are registers
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; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE ***
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%6:vreg_64 = REG_SEQUENCE %0, %1
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; Register and subreg index operand order swapped
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; CHECK: *** Bad machine code: Invalid register operand for REG_SEQUENCE ***
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; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE ***
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%7:vreg_64 = REG_SEQUENCE %subreg.sub0, %0, %subreg.sub1, %1
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; Invalid subreg index constants
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; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE ***
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; CHECK: - instruction: %8:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.0, %1:vgpr_32, %subreg.99999
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; CHECK-NEXT: operand 2: 0
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; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE ***
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; CHECK: instruction: %8:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.0, %1:vgpr_32, %subreg.99999
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; CHECK-NEXT: operand 4: 99999
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%8:vreg_64 = REG_SEQUENCE %0, 0, %1, 99999
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...
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