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The first patch supported only LMUL=1 types. This patch supports LMUL!=1. LMUL is length multiplier that allows multiple vector registers to be treated as one large register or a fraction of a single vector register. Supported values for LMUL are 1/8, 1/4, 1/2, 1, 2, 4, and 8. An LMUL=2 type will be twice as large as an LMUL=1 type. An LMUL=1/2 type will be half the size as an LMUL=1 type. Type name with "m2" is LMUL=2, "m4" is LMUL=4. Type name with "mf2" is LMUL=1/2, "mf4" is LMUL=1/4. For the LMUL!=1 types the user will need to scale __riscv_v_fixed_vlen by the LMUL before passing to the attribute. Reviewed By: aaron.ballman Differential Revision: https://reviews.llvm.org/D150926
147 lines
7.7 KiB
C
147 lines
7.7 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 -S -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s
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// REQUIRES: riscv-registered-target
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#include <riscv_vector.h>
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typedef __rvv_int8m1_t vint8m1_t;
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typedef __rvv_uint8m1_t vuint8m1_t;
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typedef __rvv_int16m1_t vint16m1_t;
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typedef __rvv_uint16m1_t vuint16m1_t;
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typedef __rvv_int32m1_t vint32m1_t;
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typedef __rvv_uint32m1_t vuint32m1_t;
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typedef __rvv_int64m1_t vint64m1_t;
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typedef __rvv_uint64m1_t vuint64m1_t;
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typedef __rvv_float32m1_t vfloat32m1_t;
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typedef __rvv_float64m1_t vfloat64m1_t;
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typedef __rvv_int8m2_t vint8m2_t;
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typedef __rvv_uint8m2_t vuint8m2_t;
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typedef __rvv_int16m2_t vint16m2_t;
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typedef __rvv_uint16m2_t vuint16m2_t;
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typedef __rvv_int32m2_t vint32m2_t;
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typedef __rvv_uint32m2_t vuint32m2_t;
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typedef __rvv_int64m2_t vint64m2_t;
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typedef __rvv_uint64m2_t vuint64m2_t;
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typedef __rvv_float32m2_t vfloat32m2_t;
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typedef __rvv_float64m2_t vfloat64m2_t;
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typedef vint32m1_t fixed_int32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vint32m2_t fixed_int32m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen * 2)));
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fixed_int32m1_t global_vec;
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fixed_int32m2_t global_vec_m2;
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// CHECK-LABEL: @test_ptr_to_global(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[RETVAL:%.*]] = alloca <8 x i32>, align 8
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// CHECK-NEXT: [[GLOBAL_VEC_PTR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: store ptr @global_vec, ptr [[GLOBAL_VEC_PTR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GLOBAL_VEC_PTR]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[TMP0]], align 8
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// CHECK-NEXT: store <8 x i32> [[TMP1]], ptr [[RETVAL]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8
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// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> undef, <8 x i32> [[TMP2]], i64 0)
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// CHECK-NEXT: ret <vscale x 2 x i32> [[CASTSCALABLESVE]]
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//
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fixed_int32m1_t test_ptr_to_global() {
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fixed_int32m1_t *global_vec_ptr;
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global_vec_ptr = &global_vec;
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return *global_vec_ptr;
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}
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//
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// Test casting pointer from fixed-length array to scalable vector.
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// CHECK-LABEL: @array_arg(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[RETVAL:%.*]] = alloca <8 x i32>, align 8
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// CHECK-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: store ptr [[ARR:%.*]], ptr [[ARR_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8
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// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds <8 x i32>, ptr [[TMP0]], i64 0
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// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[ARRAYIDX]], align 8
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// CHECK-NEXT: store <8 x i32> [[TMP1]], ptr [[RETVAL]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8
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// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> undef, <8 x i32> [[TMP2]], i64 0)
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// CHECK-NEXT: ret <vscale x 2 x i32> [[CASTSCALABLESVE]]
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//
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fixed_int32m1_t array_arg(fixed_int32m1_t arr[]) {
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return arr[0];
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}
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// CHECK-LABEL: @test_cast(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[RETVAL:%.*]] = alloca <8 x i32>, align 8
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// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca <vscale x 2 x i32>, align 4
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// CHECK-NEXT: store <vscale x 2 x i32> [[VEC:%.*]], ptr [[VEC_ADDR]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr @global_vec, align 8
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// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> undef, <8 x i32> [[TMP0]], i64 0)
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// CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 2 x i32>, ptr [[VEC_ADDR]], align 4
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// CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[CASTSCALABLESVE]], <vscale x 2 x i32> [[TMP1]], i64 8)
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// CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> [[TMP2]], i64 0)
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// CHECK-NEXT: store <8 x i32> [[CASTFIXEDSVE]], ptr [[RETVAL]], align 8
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// CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8
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// CHECK-NEXT: [[CASTSCALABLESVE1:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> undef, <8 x i32> [[TMP3]], i64 0)
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// CHECK-NEXT: ret <vscale x 2 x i32> [[CASTSCALABLESVE1]]
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//
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fixed_int32m1_t test_cast(vint32m1_t vec) {
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return __riscv_vadd(global_vec, vec, __riscv_v_fixed_vlen/32);
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}
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// CHECK-LABEL: @test_ptr_to_global_m2(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 8
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// CHECK-NEXT: [[GLOBAL_VEC_PTR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: store ptr @global_vec_m2, ptr [[GLOBAL_VEC_PTR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GLOBAL_VEC_PTR]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[TMP0]], align 8
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// CHECK-NEXT: store <16 x i32> [[TMP1]], ptr [[RETVAL]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr [[RETVAL]], align 8
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// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v16i32(<vscale x 2 x i32> undef, <16 x i32> [[TMP2]], i64 0)
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// CHECK-NEXT: ret <vscale x 2 x i32> [[CASTSCALABLESVE]]
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//
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fixed_int32m2_t test_ptr_to_global_m2() {
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fixed_int32m2_t *global_vec_ptr;
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global_vec_ptr = &global_vec_m2;
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return *global_vec_ptr;
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}
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//
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// Test casting pointer from fixed-length array to scalable vector.
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// CHECK-LABEL: @array_arg_m2(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 8
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// CHECK-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: store ptr [[ARR:%.*]], ptr [[ARR_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8
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// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds <16 x i32>, ptr [[TMP0]], i64 0
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// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[ARRAYIDX]], align 8
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// CHECK-NEXT: store <16 x i32> [[TMP1]], ptr [[RETVAL]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr [[RETVAL]], align 8
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// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v16i32(<vscale x 2 x i32> undef, <16 x i32> [[TMP2]], i64 0)
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// CHECK-NEXT: ret <vscale x 2 x i32> [[CASTSCALABLESVE]]
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//
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fixed_int32m2_t array_arg_m2(fixed_int32m2_t arr[]) {
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return arr[0];
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}
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// CHECK-LABEL: @test_cast_m2(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 8
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// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca <vscale x 4 x i32>, align 4
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// CHECK-NEXT: store <vscale x 4 x i32> [[VEC:%.*]], ptr [[VEC_ADDR]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr @global_vec_m2, align 8
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// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP0]], i64 0)
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// CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 4 x i32>, ptr [[VEC_ADDR]], align 4
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// CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[CASTSCALABLESVE]], <vscale x 4 x i32> [[TMP1]], i64 16)
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// CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TMP2]], i64 0)
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// CHECK-NEXT: store <16 x i32> [[CASTFIXEDSVE]], ptr [[RETVAL]], align 8
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// CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr [[RETVAL]], align 8
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// CHECK-NEXT: [[CASTSCALABLESVE1:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v16i32(<vscale x 2 x i32> undef, <16 x i32> [[TMP3]], i64 0)
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// CHECK-NEXT: ret <vscale x 2 x i32> [[CASTSCALABLESVE1]]
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//
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fixed_int32m2_t test_cast_m2(vint32m2_t vec) {
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return __riscv_vadd(global_vec_m2, vec, __riscv_v_fixed_vlen/16);
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}
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