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42e79d9771
This allows the user to set the size of the scalable vector so they can be used in structs and as the type of global variables. This works by representing the type as a fixed vector instead of a scalable vector in IR. Conversions to and from scalable vectors are made where necessary like function arguments/returns and intrinsics. This features has been requested here https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/176 I know arm_sve_vector_bits is used by the Eigen library so this could be used to port Eigen to RVV. This patch adds a new preprocessor define `__riscv_v_fixed_vlen` that is set when -mrvv_vector_bits is passed on the command line. The code is largely based on the AArch64 code. A lot of code was copy/pasted and then modiied to RVV. There may be some opportunities for sharing. This first patch only supports the LMUL=1 types. Additional changes will be needed to support other LMULs. I have also not supported mask vectors. Differential Revision: https://reviews.llvm.org/D145088
135 lines
5.4 KiB
C
135 lines
5.4 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d \
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// RUN: -target-feature +f -target-feature +d -disable-O0-optnone \
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// RUN: -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - %s | \
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// RUN: opt -S -passes=sroa | FileCheck %s
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// REQUIRES: riscv-registered-target
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#include <stddef.h>
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#include <stdint.h>
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typedef __rvv_int8m1_t vint8m1_t;
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typedef __rvv_uint8m1_t vuint8m1_t;
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typedef __rvv_int16m1_t vint16m1_t;
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typedef __rvv_uint16m1_t vuint16m1_t;
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typedef __rvv_int32m1_t vint32m1_t;
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typedef __rvv_uint32m1_t vuint32m1_t;
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typedef __rvv_int64m1_t vint64m1_t;
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typedef __rvv_uint64m1_t vuint64m1_t;
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typedef __rvv_float32m1_t vfloat32m1_t;
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typedef __rvv_float64m1_t vfloat64m1_t;
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typedef vint8m1_t fixed_int8m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vint16m1_t fixed_int16m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vint32m1_t fixed_int32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vint64m1_t fixed_int64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vuint8m1_t fixed_uint8m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vuint16m1_t fixed_uint16m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vuint32m1_t fixed_uint32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vuint64m1_t fixed_uint64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vfloat32m1_t fixed_float32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vfloat64m1_t fixed_float64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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// CHECK-LABEL: @subscript_int8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A:%.*]] = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> [[A_COERCE:%.*]], i64 0)
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// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <32 x i8> [[A]], i64 [[B:%.*]]
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// CHECK-NEXT: ret i8 [[VECEXT]]
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//
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int8_t subscript_int8(fixed_int8m1_t a, size_t b) {
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return a[b];
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}
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// CHECK-LABEL: @subscript_uint8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A:%.*]] = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> [[A_COERCE:%.*]], i64 0)
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// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <32 x i8> [[A]], i64 [[B:%.*]]
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// CHECK-NEXT: ret i8 [[VECEXT]]
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//
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uint8_t subscript_uint8(fixed_uint8m1_t a, size_t b) {
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return a[b];
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}
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// CHECK-LABEL: @subscript_int16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A:%.*]] = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> [[A_COERCE:%.*]], i64 0)
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// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <16 x i16> [[A]], i64 [[B:%.*]]
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// CHECK-NEXT: ret i16 [[VECEXT]]
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//
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int16_t subscript_int16(fixed_int16m1_t a, size_t b) {
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return a[b];
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}
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// CHECK-LABEL: @subscript_uint16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A:%.*]] = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> [[A_COERCE:%.*]], i64 0)
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// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <16 x i16> [[A]], i64 [[B:%.*]]
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// CHECK-NEXT: ret i16 [[VECEXT]]
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//
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uint16_t subscript_uint16(fixed_uint16m1_t a, size_t b) {
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return a[b];
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}
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// CHECK-LABEL: @subscript_int32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> [[A_COERCE:%.*]], i64 0)
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// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <8 x i32> [[A]], i64 [[B:%.*]]
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// CHECK-NEXT: ret i32 [[VECEXT]]
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//
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int32_t subscript_int32(fixed_int32m1_t a, size_t b) {
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return a[b];
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}
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// CHECK-LABEL: @subscript_uint32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> [[A_COERCE:%.*]], i64 0)
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// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <8 x i32> [[A]], i64 [[B:%.*]]
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// CHECK-NEXT: ret i32 [[VECEXT]]
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//
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uint32_t subscript_uint32(fixed_uint32m1_t a, size_t b) {
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return a[b];
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}
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// CHECK-LABEL: @subscript_int64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> [[A_COERCE:%.*]], i64 0)
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// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x i64> [[A]], i64 [[B:%.*]]
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// CHECK-NEXT: ret i64 [[VECEXT]]
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//
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int64_t subscript_int64(fixed_int64m1_t a, size_t b) {
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return a[b];
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}
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// CHECK-LABEL: @subscript_uint64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> [[A_COERCE:%.*]], i64 0)
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// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x i64> [[A]], i64 [[B:%.*]]
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// CHECK-NEXT: ret i64 [[VECEXT]]
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//
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uint64_t subscript_uint64(fixed_uint64m1_t a, size_t b) {
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return a[b];
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}
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// CHECK-LABEL: @subscript_float32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A:%.*]] = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> [[A_COERCE:%.*]], i64 0)
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// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <8 x float> [[A]], i64 [[B:%.*]]
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// CHECK-NEXT: ret float [[VECEXT]]
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//
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float subscript_float32(fixed_float32m1_t a, size_t b) {
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return a[b];
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}
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// CHECK-LABEL: @subscript_float64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A:%.*]] = call <4 x double> @llvm.vector.extract.v4f64.nxv1f64(<vscale x 1 x double> [[A_COERCE:%.*]], i64 0)
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// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x double> [[A]], i64 [[B:%.*]]
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// CHECK-NEXT: ret double [[VECEXT]]
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//
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double subscript_float64(fixed_float64m1_t a, size_t b) {
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return a[b];
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}
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