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This patch adds masking support for more contraction flavors including those with any combiner operation (add, mul, min, max, and, or, etc.) and regular matmul contractions. Combiner operations that are performing vertical reductions (and, therefore, they are not represented with a horizontal reduction operation) can be executed unmasked. However, the previous value of the accumulator must be propagated for lanes that shouldn't accumulate. We achieve this goal by introducing a select operation after the accumulator to choose between the combined and the previous accumulator value. This design decision is made to avoid introducing masking support to all the arithmetic and logical operations in the Arith dialect. VP intrinsics do not support pass-thru values either so we would have to generate the same sequence when lowering to LLVM. The op + select pattern is peepholed by some backend with native masking support for those operations. Consequently, this patch removes masking support from the vector.fma operation to follow the same approach for all the combiner operations. Reviewed By: ThomasRaoux Differential Revision: https://reviews.llvm.org/D144239
Multi-Level Intermediate Representation
See https://mlir.llvm.org/ for more information.