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8771023543
llvm-reduce run its full pass sequence up to 5 times, instead of just once Differential Revision: https://reviews.llvm.org/D128284
44 lines
1.2 KiB
YAML
44 lines
1.2 KiB
YAML
# REQUIRES: amdgpu-registered-target
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# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir -mtriple=amdgcn-amd-amdhsa --delta-passes=instructions --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
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# RUN: FileCheck --check-prefix=RESULT %s < %t
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# Make sure there's no crash with unreachable blocks.
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# CHECK-INTERESTINGNESS: S_NOP
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# RESULT: bb.0:
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# RESULT: %{{[0-9]+}}:vgpr_32 = IMPLICIT_DEF
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# RESULT-NEXT: %{{[0-9]+}}:sreg_64 = IMPLICIT_DEF
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# RESULT-NEXT: %{{[0-9]+}}:vreg_64 = IMPLICIT_DEF
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# RESULT-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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# RESULT-NEXT: S_BRANCH %bb.3
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# RESULT: bb.1:
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# RESULT-NEXT: S_BRANCH %bb.3
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# RESULT: bb.2:
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# RESULT-NEXT: S_NOP 0, implicit %{{[0-9]+}}, implicit killed %{{[0-9]+}}, implicit %{{[0-9]+}}
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---
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name: unreachable_block
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tracksRegLiveness: true
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body: |
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bb.0:
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%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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S_BRANCH %bb.3
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bb.1:
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%1:sreg_64 = S_MOV_B64 0
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S_BRANCH %bb.3
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bb.2:
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%2:vreg_64 = IMPLICIT_DEF
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S_NOP 0, implicit %0, implicit killed %2, implicit %1
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S_BRANCH %bb.3
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bb.3:
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...
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