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500846d2f5
Introduce Code Object V6 in Clang, LLD, Flang and LLVM. This is the same as V5 except a new "generic version" flag can be present in EFLAGS. This is related to new generic targets that'll be added in a follow-up patch. It's also likely V6 will have new changes (possibly new metadata entries) added later. Docs change are part of the follow-up patch #76955
78 lines
4.3 KiB
Plaintext
78 lines
4.3 KiB
Plaintext
// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa \
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// RUN: -fcuda-is-device -mcode-object-version=4 -emit-llvm -o - -x hip %s \
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// RUN: | FileCheck -check-prefix=PRECOV5 %s
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa \
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// RUN: -fcuda-is-device -emit-llvm -o - -x hip %s \
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// RUN: | FileCheck -check-prefix=COV5 %s
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa \
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// RUN: -fcuda-is-device -mcode-object-version=6 -emit-llvm -o - -x hip %s \
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// RUN: | FileCheck -check-prefix=COV5 %s
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa \
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// RUN: -fcuda-is-device -mcode-object-version=none -emit-llvm -o - -x hip %s \
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// RUN: | FileCheck -check-prefix=COVNONE %s
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#include "Inputs/cuda.h"
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// PRECOV5-LABEL: test_get_workgroup_size
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// PRECOV5: call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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// PRECOV5: getelementptr i8, ptr addrspace(4) %{{.*}}, i32 4
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// PRECOV5: load i16, ptr addrspace(4) %{{.*}}, align 2, !range [[$WS_RANGE:![0-9]*]], !invariant.load{{.*}}, !noundef
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// PRECOV5: getelementptr i8, ptr addrspace(4) %{{.*}}, i32 6
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// PRECOV5: load i16, ptr addrspace(4) %{{.*}}, align 2, !range [[$WS_RANGE:![0-9]*]], !invariant.load{{.*}}, !noundef
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// PRECOV5: getelementptr i8, ptr addrspace(4) %{{.*}}, i32 8
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// PRECOV5: load i16, ptr addrspace(4) %{{.*}}, align 2, !range [[$WS_RANGE:![0-9]*]], !invariant.load{{.*}}, !noundef
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// COV5-LABEL: test_get_workgroup_size
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// COV5: call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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// COV5: getelementptr i8, ptr addrspace(4) %{{.*}}, i32 12
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// COV5: load i16, ptr addrspace(4) %{{.*}}, align 2, !range [[$WS_RANGE:![0-9]*]], !invariant.load{{.*}}, !noundef
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// COV5: getelementptr i8, ptr addrspace(4) %{{.*}}, i32 14
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// COV5: load i16, ptr addrspace(4) %{{.*}}, align 2, !range [[$WS_RANGE:![0-9]*]], !invariant.load{{.*}}, !noundef
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// COV5: getelementptr i8, ptr addrspace(4) %{{.*}}, i32 16
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// COV5: load i16, ptr addrspace(4) %{{.*}}, align 2, !range [[$WS_RANGE:![0-9]*]], !invariant.load{{.*}}, !noundef
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// COVNONE-LABEL: test_get_workgroup_size
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// COVNONE: load i32, ptr addrspace(4) @__oclc_ABI_version
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// COVNONE: [[ABI5_X:%.*]] = icmp sge i32 %{{.*}}, 500
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// COVNONE: call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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// COVNONE: [[GEP_5_X:%.*]] = getelementptr i8, ptr addrspace(4) %{{.*}}, i32 12
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// COVNONE: call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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// COVNONE: [[GEP_4_X:%.*]] = getelementptr i8, ptr addrspace(4) %{{.*}}, i32 4
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// COVNONE: select i1 [[ABI5_X]], ptr addrspace(4) [[GEP_5_X]], ptr addrspace(4) [[GEP_4_X]]
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// COVNONE: load i16, ptr addrspace(4) %{{.*}}, align 2, !range [[$WS_RANGE:![0-9]*]], !invariant.load{{.*}}, !noundef
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// COVNONE: load i32, ptr addrspace(4) @__oclc_ABI_version
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// COVNONE: [[ABI5_Y:%.*]] = icmp sge i32 %{{.*}}, 500
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// COVNONE: call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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// COVNONE: [[GEP_5_Y:%.*]] = getelementptr i8, ptr addrspace(4) %{{.*}}, i32 14
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// COVNONE: call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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// COVNONE: [[GEP_4_Y:%.*]] = getelementptr i8, ptr addrspace(4) %{{.*}}, i32 6
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// COVNONE: select i1 [[ABI5_Y]], ptr addrspace(4) [[GEP_5_Y]], ptr addrspace(4) [[GEP_4_Y]]
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// COVNONE: load i16, ptr addrspace(4) %{{.*}}, align 2, !range [[$WS_RANGE:![0-9]*]], !invariant.load{{.*}}, !noundef
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// COVNONE: load i32, ptr addrspace(4) @__oclc_ABI_version
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// COVNONE: [[ABI5_Z:%.*]] = icmp sge i32 %{{.*}}, 500
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// COVNONE: call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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// COVNONE: [[GEP_5_Z:%.*]] = getelementptr i8, ptr addrspace(4) %{{.*}}, i32 16
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// COVNONE: call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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// COVNONE: [[GEP_4_Z:%.*]] = getelementptr i8, ptr addrspace(4) %{{.*}}, i32 8
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// COVNONE: select i1 [[ABI5_Z]], ptr addrspace(4) [[GEP_5_Z]], ptr addrspace(4) [[GEP_4_Z]]
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// COVNONE: load i16, ptr addrspace(4) %{{.*}}, align 2, !range [[$WS_RANGE:![0-9]*]], !invariant.load{{.*}}, !noundef
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__device__ void test_get_workgroup_size(int d, int *out)
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{
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switch (d) {
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case 0: *out = __builtin_amdgcn_workgroup_size_x(); break;
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case 1: *out = __builtin_amdgcn_workgroup_size_y(); break;
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case 2: *out = __builtin_amdgcn_workgroup_size_z(); break;
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default: *out = 0;
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}
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}
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// CHECK-DAG: [[$WS_RANGE]] = !{i16 1, i16 1025}
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