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bd860f9864
Adds NVVM intrinsics, NVPTX codegen and Clang builtins for `redux.sync` f32 instructions introduced in ptx8.6 for sm_100a. Tests added in `CodeGen/NVPTX/redux-sync.ll` and `CodeGenCUDA/redux-builtins.cu` and verified through ptxas 12.8.0. PTX Spec Reference: https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-redux-sync
35 lines
1.4 KiB
Plaintext
35 lines
1.4 KiB
Plaintext
// RUN: %clang_cc1 "-triple" "nvptx-nvidia-cuda" "-target-feature" "+ptx86" "-target-cpu" "sm_100a" -emit-llvm -fcuda-is-device -o - %s | FileCheck %s
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// RUN: %clang_cc1 "-triple" "nvptx64-nvidia-cuda" "-target-feature" "+ptx86" "-target-cpu" "sm_100a" -emit-llvm -fcuda-is-device -o - %s | FileCheck %s
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// CHECK: define{{.*}} void @_Z6kernelPf(ptr noundef %out_f)
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__attribute__((global)) void kernel(float* out_f) {
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float a = 3.0;
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int i = 0;
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out_f[i++] = __nvvm_redux_sync_fmin(a, 0xFF);
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// CHECK: call contract float @llvm.nvvm.redux.sync.fmin
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out_f[i++] = __nvvm_redux_sync_fmin_abs(a, 0xFF);
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// CHECK: call contract float @llvm.nvvm.redux.sync.fmin.abs
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out_f[i++] = __nvvm_redux_sync_fmin_NaN(a, 0xF0);
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// CHECK: call contract float @llvm.nvvm.redux.sync.fmin.NaN
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out_f[i++] = __nvvm_redux_sync_fmin_abs_NaN(a, 0x0F);
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// CHECK: call contract float @llvm.nvvm.redux.sync.fmin.abs.NaN
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out_f[i++] = __nvvm_redux_sync_fmax(a, 0xFF);
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// CHECK: call contract float @llvm.nvvm.redux.sync.fmax
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out_f[i++] = __nvvm_redux_sync_fmax_abs(a, 0x01);
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// CHECK: call contract float @llvm.nvvm.redux.sync.fmax.abs
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out_f[i++] = __nvvm_redux_sync_fmax_NaN(a, 0xF1);
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// CHECK: call contract float @llvm.nvvm.redux.sync.fmax.NaN
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out_f[i++] = __nvvm_redux_sync_fmax_abs_NaN(a, 0x10);
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// CHECK: call contract float @llvm.nvvm.redux.sync.fmax.abs.NaN
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// CHECK: ret void
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}
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