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f6e11a36c4
Summary: Writing support for three ACLE functions: unsigned int __cls(uint32_t x) unsigned int __clsl(unsigned long x) unsigned int __clsll(uint64_t x) CLS stands for "Count number of leading sign bits". In AArch64, these two intrinsics can be translated into the 'cls' instruction directly. In AArch32, on the other hand, this functionality is achieved by implementing it in terms of clz (count number of leading zeros). Reviewers: compnerd Reviewed By: compnerd Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D69250
277 lines
7.1 KiB
C
277 lines
7.1 KiB
C
// RUN: %clang_cc1 -Wall -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
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#include <stdint.h>
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void *f0()
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{
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return __builtin_thread_pointer();
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}
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void f1(char *a, char *b) {
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// CHECK: call {{.*}} @__clear_cache
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__clear_cache(a,b);
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}
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float test_vcvtrf0(float f) {
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// CHECK: call float @llvm.arm.vcvtr.f32(float %f)
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return __builtin_arm_vcvtr_f(f, 0);
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}
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float test_vcvtrf1(float f) {
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// CHECK: call float @llvm.arm.vcvtru.f32(float %f)
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return __builtin_arm_vcvtr_f(f, 1);
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}
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double test_vcvtrd0(double d) {
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// CHECK: call float @llvm.arm.vcvtr.f64(double %d)
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return __builtin_arm_vcvtr_d(d, 0);
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}
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double test_vcvtrd1(double d) {
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// call float @llvm.arm.vcvtru.f64(double %d)
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return __builtin_arm_vcvtr_d(d, 1);
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}
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void test_eh_return_data_regno()
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{
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// CHECK: store volatile i32 0
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// CHECK: store volatile i32 1
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volatile int res;
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res = __builtin_eh_return_data_regno(0);
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res = __builtin_eh_return_data_regno(1);
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}
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void nop() {
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// CHECK: call {{.*}} @llvm.arm.hint(i32 0)
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__builtin_arm_nop();
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}
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void yield() {
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// CHECK: call {{.*}} @llvm.arm.hint(i32 1)
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__builtin_arm_yield();
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}
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void wfe() {
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// CHECK: call {{.*}} @llvm.arm.hint(i32 2)
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__builtin_arm_wfe();
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}
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void wfi() {
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// CHECK: call {{.*}} @llvm.arm.hint(i32 3)
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__builtin_arm_wfi();
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}
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void sev() {
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// CHECK: call {{.*}} @llvm.arm.hint(i32 4)
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__builtin_arm_sev();
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}
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void sevl() {
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// CHECK: call {{.*}} @llvm.arm.hint(i32 5)
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__builtin_arm_sevl();
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}
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void dbg() {
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// CHECK: call {{.*}} @llvm.arm.dbg(i32 0)
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__builtin_arm_dbg(0);
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}
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void test_barrier() {
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//CHECK: call {{.*}} @llvm.arm.dmb(i32 1)
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//CHECK: call {{.*}} @llvm.arm.dsb(i32 2)
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//CHECK: call {{.*}} @llvm.arm.isb(i32 3)
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__builtin_arm_dmb(1);
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__builtin_arm_dsb(2);
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__builtin_arm_isb(3);
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}
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unsigned rbit(unsigned a) {
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// CHECK: call {{.*}} @llvm.bitreverse.i32(i32 %a)
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return __builtin_arm_rbit(a);
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}
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void prefetch(int i) {
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__builtin_arm_prefetch(&i, 0, 1);
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// CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* %{{.*}}, i32 0, i32 3, i32 1)
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__builtin_arm_prefetch(&i, 1, 1);
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// CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* %{{.*}}, i32 1, i32 3, i32 1)
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__builtin_arm_prefetch(&i, 1, 0);
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// CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* %{{.*}}, i32 1, i32 3, i32 0)
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}
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void ldc(const void *i) {
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// CHECK: define void @ldc(i8* %i)
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// CHECK: call void @llvm.arm.ldc(i32 1, i32 2, i8* %i)
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// CHECK-NEXT: ret void
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__builtin_arm_ldc(1, 2, i);
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}
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void ldcl(const void *i) {
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// CHECK: define void @ldcl(i8* %i)
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// CHECK: call void @llvm.arm.ldcl(i32 1, i32 2, i8* %i)
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// CHECK-NEXT: ret void
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__builtin_arm_ldcl(1, 2, i);
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}
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void ldc2(const void *i) {
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// CHECK: define void @ldc2(i8* %i)
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// CHECK: call void @llvm.arm.ldc2(i32 1, i32 2, i8* %i)
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// CHECK-NEXT: ret void
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__builtin_arm_ldc2(1, 2, i);
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}
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void ldc2l(const void *i) {
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// CHECK: define void @ldc2l(i8* %i)
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// CHECK: call void @llvm.arm.ldc2l(i32 1, i32 2, i8* %i)
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// CHECK-NEXT: ret void
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__builtin_arm_ldc2l(1, 2, i);
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}
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void stc(void *i) {
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// CHECK: define void @stc(i8* %i)
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// CHECK: call void @llvm.arm.stc(i32 1, i32 2, i8* %i)
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// CHECK-NEXT: ret void
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__builtin_arm_stc(1, 2, i);
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}
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void stcl(void *i) {
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// CHECK: define void @stcl(i8* %i)
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// CHECK: call void @llvm.arm.stcl(i32 1, i32 2, i8* %i)
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// CHECK-NEXT: ret void
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__builtin_arm_stcl(1, 2, i);
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}
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void stc2(void *i) {
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// CHECK: define void @stc2(i8* %i)
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// CHECK: call void @llvm.arm.stc2(i32 1, i32 2, i8* %i)
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// CHECK-NEXT: ret void
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__builtin_arm_stc2(1, 2, i);
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}
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void stc2l(void *i) {
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// CHECK: define void @stc2l(i8* %i)
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// CHECK: call void @llvm.arm.stc2l(i32 1, i32 2, i8* %i)
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// CHECK-NEXT: ret void
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__builtin_arm_stc2l(1, 2, i);
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}
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void cdp() {
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// CHECK: define void @cdp()
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// CHECK: call void @llvm.arm.cdp(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
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// CHECK-NEXT: ret void
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__builtin_arm_cdp(1, 2, 3, 4, 5, 6);
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}
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void cdp2() {
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// CHECK: define void @cdp2()
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// CHECK: call void @llvm.arm.cdp2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
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// CHECK-NEXT: ret void
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__builtin_arm_cdp2(1, 2, 3, 4, 5, 6);
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}
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unsigned mrc() {
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// CHECK: define i32 @mrc()
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// CHECK: [[R:%.*]] = call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3)
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// CHECK-NEXT: ret i32 [[R]]
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return __builtin_arm_mrc(15, 0, 13, 0, 3);
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}
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unsigned mrc2() {
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// CHECK: define i32 @mrc2()
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// CHECK: [[R:%.*]] = call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3)
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// CHECK-NEXT: ret i32 [[R]]
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return __builtin_arm_mrc2(15, 0, 13, 0, 3);
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}
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void mcr(unsigned a) {
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// CHECK: define void @mcr(i32 [[A:%.*]])
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// CHECK: call void @llvm.arm.mcr(i32 15, i32 0, i32 [[A]], i32 13, i32 0, i32 3)
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__builtin_arm_mcr(15, 0, a, 13, 0, 3);
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}
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void mcr2(unsigned a) {
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// CHECK: define void @mcr2(i32 [[A:%.*]])
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// CHECK: call void @llvm.arm.mcr2(i32 15, i32 0, i32 [[A]], i32 13, i32 0, i32 3)
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__builtin_arm_mcr2(15, 0, a, 13, 0, 3);
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}
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void mcrr(uint64_t a) {
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// CHECK: define void @mcrr(i64 %{{.*}})
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// CHECK: call void @llvm.arm.mcrr(i32 15, i32 0, i32 %{{[0-9]+}}, i32 %{{[0-9]+}}, i32 0)
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__builtin_arm_mcrr(15, 0, a, 0);
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}
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void mcrr2(uint64_t a) {
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// CHECK: define void @mcrr2(i64 %{{.*}})
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// CHECK: call void @llvm.arm.mcrr2(i32 15, i32 0, i32 %{{[0-9]+}}, i32 %{{[0-9]+}}, i32 0)
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__builtin_arm_mcrr2(15, 0, a, 0);
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}
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uint64_t mrrc() {
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// CHECK: define i64 @mrrc()
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// CHECK: call { i32, i32 } @llvm.arm.mrrc(i32 15, i32 0, i32 0)
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return __builtin_arm_mrrc(15, 0, 0);
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}
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uint64_t mrrc2() {
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// CHECK: define i64 @mrrc2()
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// CHECK: call { i32, i32 } @llvm.arm.mrrc2(i32 15, i32 0, i32 0)
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return __builtin_arm_mrrc2(15, 0, 0);
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}
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unsigned rsr() {
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// CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_register.i32(metadata ![[M0:.*]])
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// CHECK-NEXT: ret i32 [[V0]]
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return __builtin_arm_rsr("cp1:2:c3:c4:5");
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}
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unsigned long long rsr64() {
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// CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_register.i64(metadata ![[M1:.*]])
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// CHECK-NEXT: ret i64 [[V0]]
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return __builtin_arm_rsr64("cp1:2:c3");
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}
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void *rsrp() {
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// CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_register.i32(metadata ![[M2:.*]])
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// CHECK-NEXT: [[V1:[%A-Za-z0-9.]+]] = inttoptr i32 [[V0]] to i8*
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// CHECK-NEXT: ret i8* [[V1]]
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return __builtin_arm_rsrp("sysreg");
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}
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void wsr(unsigned v) {
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// CHECK: call void @llvm.write_register.i32(metadata ![[M0]], i32 %v)
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__builtin_arm_wsr("cp1:2:c3:c4:5", v);
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}
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void wsr64(unsigned long long v) {
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// CHECK: call void @llvm.write_register.i64(metadata ![[M1]], i64 %v)
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__builtin_arm_wsr64("cp1:2:c3", v);
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}
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void wsrp(void *v) {
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// CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint i8* %v to i32
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// CHECK-NEXT: call void @llvm.write_register.i32(metadata ![[M2]], i32 [[V0]])
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__builtin_arm_wsrp("sysreg", v);
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}
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unsigned int cls(uint32_t v) {
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// CHECK: call i32 @llvm.arm.cls(i32 %v)
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return __builtin_arm_cls(v);
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}
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unsigned int clsl(unsigned long v) {
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// CHECK: call i32 @llvm.arm.cls(i32 %v)
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return __builtin_arm_cls(v);
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}
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unsigned int clsll(uint64_t v) {
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// CHECK: call i32 @llvm.arm.cls64(i64 %v)
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return __builtin_arm_cls64(v);
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}
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// CHECK: ![[M0]] = !{!"cp1:2:c3:c4:5"}
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// CHECK: ![[M1]] = !{!"cp1:2:c3"}
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// CHECK: ![[M2]] = !{!"sysreg"}
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