Praveen Batra 3a3190fbce Fix typo in Pallas TPU matmul doc. I think the logical layout of the input array is non-transposed, rather than transposed? ...

PiperOrigin-RevId: 686151692

2024-10-15 10:23:39 -07:00

..

tpu

Fix typo in Pallas TPU matmul doc. I think the logical layout of the input array is non-transposed, rather than transposed?

2024-10-15 10:23:39 -07:00

async_note.md

Fix make_remote_async_copy -> make_async_remote_copy in async doc.

2024-09-25 13:39:39 -07:00

CHANGELOG.md

[Pallas] Add runtime assert via checkify.check. This check will halt the TPU if triggered, meaning that we would need to restart the program to recover.

2024-10-11 13:34:04 -07:00

design.md

Changed `pl.BlockSpec to accept block_shape before index_map`

2024-07-01 14:26:08 -07:00

grid_blockspec.md

[Pallas] [Docs] Replace full urls with label-based cross references

2024-10-03 14:35:51 -07:00

index.rst

[Pallas] Add design note for async ops on TPU

2024-09-17 12:45:29 -07:00

quickstart.ipynb

[Pallas] [Docs] Replace full urls with label-based cross references

2024-10-03 14:35:51 -07:00

quickstart.md

[Pallas] [Docs] Replace full urls with label-based cross references

2024-10-03 14:35:51 -07:00